1*4882a593SmuzhiyunRegister-based I2C Bus Mux 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis binding describes an I2C bus multiplexer that uses a single register 4*4882a593Smuzhiyunto route the I2C signals. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: i2c-mux-reg 8*4882a593Smuzhiyun- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side 9*4882a593Smuzhiyun port is connected to. 10*4882a593Smuzhiyun* Standard I2C mux properties. See i2c-mux.txt in this directory. 11*4882a593Smuzhiyun* I2C child bus nodes. See i2c-mux.txt in this directory. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunOptional properties: 14*4882a593Smuzhiyun- reg: this pair of <offset size> specifies the register to control the mux. 15*4882a593Smuzhiyun The <offset size> depends on its parent node. It can be any memory-mapped 16*4882a593Smuzhiyun address. The size must be either 1, 2, or 4 bytes. If reg is omitted, the 17*4882a593Smuzhiyun resource of this device will be used. 18*4882a593Smuzhiyun- little-endian: The existence indicates the register is in little endian. 19*4882a593Smuzhiyun- big-endian: The existence indicates the register is in big endian. 20*4882a593Smuzhiyun If both little-endian and big-endian are omitted, the endianness of the 21*4882a593Smuzhiyun CPU will be used. 22*4882a593Smuzhiyun- write-only: The existence indicates the register is write-only. 23*4882a593Smuzhiyun- idle-state: value to set the muxer to when idle. When no value is 24*4882a593Smuzhiyun given, it defaults to the last value used. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunWhenever an access is made to a device on a child bus, the value set 27*4882a593Smuzhiyunin the relevant node's reg property will be output to the register. 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunIf an idle state is defined, using the idle-state (optional) property, 30*4882a593Smuzhiyunwhenever an access is not being made to a device on a child bus, the 31*4882a593Smuzhiyunregister will be set according to the idle value. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunIf an idle state is not defined, the most recently used value will be 34*4882a593Smuzhiyunleft programmed into the register. 35*4882a593Smuzhiyun 36*4882a593SmuzhiyunExample of a mux on PCIe card, the host is a powerpc SoC (big endian): 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun i2c-mux { 39*4882a593Smuzhiyun /* the <offset size> depends on the address translation 40*4882a593Smuzhiyun * of the parent device. If omitted, device resource 41*4882a593Smuzhiyun * will be used instead. The size is to determine 42*4882a593Smuzhiyun * whether iowrite32, iowrite16, or iowrite8 will be used. 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun reg = <0x6028 0x4>; 45*4882a593Smuzhiyun little-endian; /* little endian register on PCIe */ 46*4882a593Smuzhiyun compatible = "i2c-mux-reg"; 47*4882a593Smuzhiyun #address-cells = <1>; 48*4882a593Smuzhiyun #size-cells = <0>; 49*4882a593Smuzhiyun i2c-parent = <&i2c1>; 50*4882a593Smuzhiyun i2c@0 { 51*4882a593Smuzhiyun reg = <0>; 52*4882a593Smuzhiyun #address-cells = <1>; 53*4882a593Smuzhiyun #size-cells = <0>; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun si5338: clock-generator@70 { 56*4882a593Smuzhiyun compatible = "silabs,si5338"; 57*4882a593Smuzhiyun reg = <0x70>; 58*4882a593Smuzhiyun /* other stuff */ 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun i2c@1 { 63*4882a593Smuzhiyun /* data is written using iowrite32 */ 64*4882a593Smuzhiyun reg = <1>; 65*4882a593Smuzhiyun #address-cells = <1>; 66*4882a593Smuzhiyun #size-cells = <0>; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun si5338: clock-generator@70 { 69*4882a593Smuzhiyun compatible = "silabs,si5338"; 70*4882a593Smuzhiyun reg = <0x70>; 71*4882a593Smuzhiyun /* other stuff */ 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun }; 75