1*4882a593Smuzhiyun* I2C 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties : 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun - reg : Offset and length of the register set for the device 6*4882a593Smuzhiyun - compatible : should be "fsl,CHIP-i2c" where CHIP is the name of a 7*4882a593Smuzhiyun compatible processor, e.g. mpc8313, mpc8543, mpc8544, mpc5121, 8*4882a593Smuzhiyun mpc5200 or mpc5200b. For the mpc5121, an additional node 9*4882a593Smuzhiyun "fsl,mpc5121-i2c-ctrl" is required as shown in the example below. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRecommended properties : 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun - interrupts : <a b> where a is the interrupt number and b is a 14*4882a593Smuzhiyun field that represents an encoding of the sense and level 15*4882a593Smuzhiyun information for the interrupt. This should be encoded based on 16*4882a593Smuzhiyun the information in section 2) depending on the type of interrupt 17*4882a593Smuzhiyun controller you have. 18*4882a593Smuzhiyun - fsl,preserve-clocking : boolean; if defined, the clock settings 19*4882a593Smuzhiyun from the bootloader are preserved (not touched). 20*4882a593Smuzhiyun - clock-frequency : desired I2C bus clock frequency in Hz. 21*4882a593Smuzhiyun - fsl,timeout : I2C bus timeout in microseconds. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExamples : 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* MPC5121 based board */ 26*4882a593Smuzhiyun i2c@1740 { 27*4882a593Smuzhiyun #address-cells = <1>; 28*4882a593Smuzhiyun #size-cells = <0>; 29*4882a593Smuzhiyun compatible = "fsl,mpc5121-i2c", "fsl-i2c"; 30*4882a593Smuzhiyun reg = <0x1740 0x20>; 31*4882a593Smuzhiyun interrupts = <11 0x8>; 32*4882a593Smuzhiyun interrupt-parent = <&ipic>; 33*4882a593Smuzhiyun clock-frequency = <100000>; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun i2ccontrol@1760 { 37*4882a593Smuzhiyun compatible = "fsl,mpc5121-i2c-ctrl"; 38*4882a593Smuzhiyun reg = <0x1760 0x8>; 39*4882a593Smuzhiyun }; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* MPC5200B based board */ 42*4882a593Smuzhiyun i2c@3d00 { 43*4882a593Smuzhiyun #address-cells = <1>; 44*4882a593Smuzhiyun #size-cells = <0>; 45*4882a593Smuzhiyun compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c"; 46*4882a593Smuzhiyun reg = <0x3d00 0x40>; 47*4882a593Smuzhiyun interrupts = <2 15 0>; 48*4882a593Smuzhiyun interrupt-parent = <&mpc5200_pic>; 49*4882a593Smuzhiyun fsl,preserve-clocking; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* MPC8544 base board */ 53*4882a593Smuzhiyun i2c@3100 { 54*4882a593Smuzhiyun #address-cells = <1>; 55*4882a593Smuzhiyun #size-cells = <0>; 56*4882a593Smuzhiyun compatible = "fsl,mpc8544-i2c", "fsl-i2c"; 57*4882a593Smuzhiyun reg = <0x3100 0x100>; 58*4882a593Smuzhiyun interrupts = <43 2>; 59*4882a593Smuzhiyun interrupt-parent = <&mpic>; 60*4882a593Smuzhiyun clock-frequency = <400000>; 61*4882a593Smuzhiyun fsl,timeout = <10000>; 62*4882a593Smuzhiyun }; 63