1*4882a593SmuzhiyunI2C for Hisilicon hix5hd2 chipset platform 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Must be "hisilicon,hix5hd2-i2c" 5*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 6*4882a593Smuzhiyun region. 7*4882a593Smuzhiyun- interrupts: interrupt number to the cpu. 8*4882a593Smuzhiyun- #address-cells = <1>; 9*4882a593Smuzhiyun- #size-cells = <0>; 10*4882a593Smuzhiyun- clocks: phandles to input clocks. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunOptional properties: 13*4882a593Smuzhiyun- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 14*4882a593Smuzhiyun- Child nodes conforming to i2c bus binding 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExamples: 17*4882a593SmuzhiyunI2C0@f8b10000 { 18*4882a593Smuzhiyun compatible = "hisilicon,hix5hd2-i2c"; 19*4882a593Smuzhiyun reg = <0xf8b10000 0x1000>; 20*4882a593Smuzhiyun interrupts = <0 38 4>; 21*4882a593Smuzhiyun clocks = <&clock HIX5HD2_I2C0_RST>; 22*4882a593Smuzhiyun #address-cells = <1>; 23*4882a593Smuzhiyun #size-cells = <0>; 24*4882a593Smuzhiyun} 25