1*4882a593SmuzhiyunI2C for Atmel platforms 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties : 4*4882a593Smuzhiyun- compatible : Must be one of: 5*4882a593Smuzhiyun "atmel,at91rm9200-i2c", 6*4882a593Smuzhiyun "atmel,at91sam9261-i2c", 7*4882a593Smuzhiyun "atmel,at91sam9260-i2c", 8*4882a593Smuzhiyun "atmel,at91sam9g20-i2c", 9*4882a593Smuzhiyun "atmel,at91sam9g10-i2c", 10*4882a593Smuzhiyun "atmel,at91sam9x5-i2c", 11*4882a593Smuzhiyun "atmel,sama5d4-i2c", 12*4882a593Smuzhiyun "atmel,sama5d2-i2c", 13*4882a593Smuzhiyun "microchip,sam9x60-i2c". 14*4882a593Smuzhiyun- reg: physical base address of the controller and length of memory mapped 15*4882a593Smuzhiyun region. 16*4882a593Smuzhiyun- interrupts: interrupt number to the cpu. 17*4882a593Smuzhiyun- #address-cells = <1>; 18*4882a593Smuzhiyun- #size-cells = <0>; 19*4882a593Smuzhiyun- clocks: phandles to input clocks. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunOptional properties: 22*4882a593Smuzhiyun- clock-frequency: Desired I2C bus frequency in Hz, otherwise defaults to 100000 23*4882a593Smuzhiyun- dmas: A list of two dma specifiers, one for each entry in dma-names. 24*4882a593Smuzhiyun- dma-names: should contain "tx" and "rx". 25*4882a593Smuzhiyun- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO 26*4882a593Smuzhiyun capable I2C controllers. 27*4882a593Smuzhiyun- i2c-sda-hold-time-ns: TWD hold time, only available for: 28*4882a593Smuzhiyun "atmel,sama5d4-i2c", 29*4882a593Smuzhiyun "atmel,sama5d2-i2c", 30*4882a593Smuzhiyun "microchip,sam9x60-i2c". 31*4882a593Smuzhiyun- scl-gpios: specify the gpio related to SCL pin 32*4882a593Smuzhiyun- sda-gpios: specify the gpio related to SDA pin 33*4882a593Smuzhiyun- pinctrl: add extra pinctrl to configure i2c pins to gpio function for i2c 34*4882a593Smuzhiyun bus recovery, call it "gpio" state 35*4882a593Smuzhiyun- Child nodes conforming to i2c bus binding 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun 38*4882a593SmuzhiyunExamples : 39*4882a593Smuzhiyun 40*4882a593Smuzhiyuni2c0: i2c@fff84000 { 41*4882a593Smuzhiyun compatible = "atmel,at91sam9g20-i2c"; 42*4882a593Smuzhiyun reg = <0xfff84000 0x100>; 43*4882a593Smuzhiyun interrupts = <12 4 6>; 44*4882a593Smuzhiyun #address-cells = <1>; 45*4882a593Smuzhiyun #size-cells = <0>; 46*4882a593Smuzhiyun clocks = <&twi0_clk>; 47*4882a593Smuzhiyun clock-frequency = <400000>; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun 24c512@50 { 50*4882a593Smuzhiyun compatible = "atmel,24c512"; 51*4882a593Smuzhiyun reg = <0x50>; 52*4882a593Smuzhiyun pagesize = <128>; 53*4882a593Smuzhiyun } 54*4882a593Smuzhiyun} 55*4882a593Smuzhiyun 56*4882a593Smuzhiyuni2c0: i2c@f8034600 { 57*4882a593Smuzhiyun compatible = "atmel,sama5d2-i2c"; 58*4882a593Smuzhiyun reg = <0xf8034600 0x100>; 59*4882a593Smuzhiyun interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>; 60*4882a593Smuzhiyun dmas = <&dma0 61*4882a593Smuzhiyun (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) 62*4882a593Smuzhiyun AT91_XDMAC_DT_PERID(11)>, 63*4882a593Smuzhiyun <&dma0 64*4882a593Smuzhiyun (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)) 65*4882a593Smuzhiyun AT91_XDMAC_DT_PERID(12)>; 66*4882a593Smuzhiyun dma-names = "tx", "rx"; 67*4882a593Smuzhiyun #address-cells = <1>; 68*4882a593Smuzhiyun #size-cells = <0>; 69*4882a593Smuzhiyun clocks = <&flx0>; 70*4882a593Smuzhiyun atmel,fifo-size = <16>; 71*4882a593Smuzhiyun i2c-sda-hold-time-ns = <336>; 72*4882a593Smuzhiyun pinctrl-names = "default", "gpio"; 73*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_i2c0>; 74*4882a593Smuzhiyun pinctrl-1 = <&pinctrl_i2c0_gpio>; 75*4882a593Smuzhiyun sda-gpios = <&pioA 30 GPIO_ACTIVE_HIGH>; 76*4882a593Smuzhiyun scl-gpios = <&pioA 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun wm8731: wm8731@1a { 79*4882a593Smuzhiyun compatible = "wm8731"; 80*4882a593Smuzhiyun reg = <0x1a>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun}; 83