1*4882a593Smuzhiyun* Altera I2C Controller 2*4882a593Smuzhiyun* This is Altera's synthesizable logic block I2C Controller for use 3*4882a593Smuzhiyun* in Altera's FPGAs. 4*4882a593Smuzhiyun 5*4882a593SmuzhiyunRequired properties : 6*4882a593Smuzhiyun - compatible : should be "altr,softip-i2c-v1.0" 7*4882a593Smuzhiyun - reg : Offset and length of the register set for the device 8*4882a593Smuzhiyun - interrupts : <IRQ> where IRQ is the interrupt number. 9*4882a593Smuzhiyun - clocks : phandle to input clock. 10*4882a593Smuzhiyun - #address-cells = <1>; 11*4882a593Smuzhiyun - #size-cells = <0>; 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunRecommended properties : 14*4882a593Smuzhiyun - clock-frequency : desired I2C bus clock frequency in Hz. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunOptional properties : 17*4882a593Smuzhiyun - fifo-size : Size of the RX and TX FIFOs in bytes. 18*4882a593Smuzhiyun - Child nodes conforming to i2c bus binding 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample : 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun i2c@100080000 { 23*4882a593Smuzhiyun compatible = "altr,softip-i2c-v1.0"; 24*4882a593Smuzhiyun reg = <0x00000001 0x00080000 0x00000040>; 25*4882a593Smuzhiyun interrupt-parent = <&intc>; 26*4882a593Smuzhiyun interrupts = <0 43 4>; 27*4882a593Smuzhiyun clocks = <&clk_0>; 28*4882a593Smuzhiyun clock-frequency = <100000>; 29*4882a593Smuzhiyun #address-cells = <1>; 30*4882a593Smuzhiyun #size-cells = <0>; 31*4882a593Smuzhiyun fifo-size = <4>; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun eeprom@51 { 34*4882a593Smuzhiyun compatible = "atmel,24c32"; 35*4882a593Smuzhiyun reg = <0x51>; 36*4882a593Smuzhiyun pagesize = <32>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40