1*4882a593SmuzhiyunBroadcom iProc I2C controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible: 6*4882a593Smuzhiyun Must be "brcm,iproc-i2c" or "brcm,iproc-nic-i2c" 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun- reg: 9*4882a593Smuzhiyun Define the base and range of the I/O address space that contain the iProc 10*4882a593Smuzhiyun I2C controller registers 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- clock-frequency: 13*4882a593Smuzhiyun This is the I2C bus clock. Need to be either 100000 or 400000 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun- #address-cells: 16*4882a593Smuzhiyun Always 1 (for I2C addresses) 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- #size-cells: 19*4882a593Smuzhiyun Always 0 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunOptional properties: 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- interrupts: 24*4882a593Smuzhiyun Should contain the I2C interrupt. For certain revisions of the I2C 25*4882a593Smuzhiyun controller, I2C interrupt is unwired to the interrupt controller. In such 26*4882a593Smuzhiyun case, this property should be left unspecified, and driver will fall back 27*4882a593Smuzhiyun to polling mode 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun- brcm,ape-hsls-addr-mask: 30*4882a593Smuzhiyun Required for "brcm,iproc-nic-i2c". Host view of address mask into the 31*4882a593Smuzhiyun 'APE' co-processor. Value must be unsigned, 32-bit 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunExample: 34*4882a593Smuzhiyun i2c0: i2c@18008000 { 35*4882a593Smuzhiyun compatible = "brcm,iproc-i2c"; 36*4882a593Smuzhiyun reg = <0x18008000 0x100>; 37*4882a593Smuzhiyun #address-cells = <1>; 38*4882a593Smuzhiyun #size-cells = <0>; 39*4882a593Smuzhiyun interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; 40*4882a593Smuzhiyun clock-frequency = <100000>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun codec: wm8750@1a { 43*4882a593Smuzhiyun compatible = "wlf,wm8750"; 44*4882a593Smuzhiyun reg = <0x1a>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun }; 47