1*4882a593SmuzhiyunASPEED AST2400/AST2500 PWM and Fan Tacho controller device driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe ASPEED PWM controller can support upto 8 PWM outputs. The ASPEED Fan Tacho 4*4882a593Smuzhiyuncontroller can support upto 16 Fan tachometer inputs. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThere can be upto 8 fans supported. Each fan can have one PWM output and 7*4882a593Smuzhiyunone/two Fan tach inputs. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties for pwm-tacho node: 10*4882a593Smuzhiyun- #address-cells : should be 1. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- #size-cells : should be 1. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- #cooling-cells: should be 2. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- reg : address and length of the register set for the device. 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun- pinctrl-names : a pinctrl state named "default" must be defined. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- pinctrl-0 : phandle referencing pin configuration of the PWM ports. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun- compatible : should be "aspeed,ast2400-pwm-tacho" for AST2400 and 23*4882a593Smuzhiyun "aspeed,ast2500-pwm-tacho" for AST2500. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun- clocks : phandle to clock provider with the clock number in the second cell 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun- resets : phandle to reset controller with the reset number in the second cell 28*4882a593Smuzhiyun 29*4882a593Smuzhiyunfan subnode format: 30*4882a593Smuzhiyun=================== 31*4882a593SmuzhiyunUnder fan subnode there can upto 8 child nodes, with each child node 32*4882a593Smuzhiyunrepresenting a fan. If there are 8 fans each fan can have one PWM port and 33*4882a593Smuzhiyunone/two Fan tach inputs. 34*4882a593SmuzhiyunFor PWM port can be configured cooling-levels to create cooling device. 35*4882a593SmuzhiyunCooling device could be bound to a thermal zone for the thermal control. 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunRequired properties for each child node: 38*4882a593Smuzhiyun- reg : should specify PWM source port. 39*4882a593Smuzhiyun integer value in the range 0 to 7 with 0 indicating PWM port A and 40*4882a593Smuzhiyun 7 indicating PWM port H. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun- cooling-levels: PWM duty cycle values in a range from 0 to 255 43*4882a593Smuzhiyun which correspond to thermal cooling states. 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun- aspeed,fan-tach-ch : should specify the Fan tach input channel. 46*4882a593Smuzhiyun integer value in the range 0 through 15, with 0 indicating 47*4882a593Smuzhiyun Fan tach channel 0 and 15 indicating Fan tach channel 15. 48*4882a593Smuzhiyun Atleast one Fan tach input channel is required. 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunExamples: 51*4882a593Smuzhiyun 52*4882a593Smuzhiyunpwm_tacho: pwmtachocontroller@1e786000 { 53*4882a593Smuzhiyun #address-cells = <1>; 54*4882a593Smuzhiyun #size-cells = <1>; 55*4882a593Smuzhiyun #cooling-cells = <2>; 56*4882a593Smuzhiyun reg = <0x1E786000 0x1000>; 57*4882a593Smuzhiyun compatible = "aspeed,ast2500-pwm-tacho"; 58*4882a593Smuzhiyun clocks = <&syscon ASPEED_CLK_APB>; 59*4882a593Smuzhiyun resets = <&syscon ASPEED_RESET_PWM>; 60*4882a593Smuzhiyun pinctrl-names = "default"; 61*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_pwm0_default &pinctrl_pwm1_default>; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun fan@0 { 64*4882a593Smuzhiyun reg = <0x00>; 65*4882a593Smuzhiyun cooling-levels = /bits/ 8 <125 151 177 203 229 255>; 66*4882a593Smuzhiyun aspeed,fan-tach-ch = /bits/ 8 <0x00>; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun fan@1 { 70*4882a593Smuzhiyun reg = <0x01>; 71*4882a593Smuzhiyun aspeed,fan-tach-ch = /bits/ 8 <0x01 0x02>; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun}; 74