1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/hwlock/st,stm32-hwspinlock.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: STMicroelectronics STM32 Hardware Spinlock bindings 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Benjamin Gaignard <benjamin.gaignard@st.com> 11*4882a593Smuzhiyun - Fabien Dessenne <fabien.dessenne@st.com> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunproperties: 14*4882a593Smuzhiyun "#hwlock-cells": 15*4882a593Smuzhiyun const: 1 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun const: st,stm32-hwspinlock 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun reg: 21*4882a593Smuzhiyun maxItems: 1 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun clocks: 24*4882a593Smuzhiyun maxItems: 1 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clock-names: 27*4882a593Smuzhiyun items: 28*4882a593Smuzhiyun - const: hsem 29*4882a593Smuzhiyun 30*4882a593Smuzhiyunrequired: 31*4882a593Smuzhiyun - "#hwlock-cells" 32*4882a593Smuzhiyun - compatible 33*4882a593Smuzhiyun - reg 34*4882a593Smuzhiyun - clocks 35*4882a593Smuzhiyun - clock-names 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunadditionalProperties: false 38*4882a593Smuzhiyun 39*4882a593Smuzhiyunexamples: 40*4882a593Smuzhiyun - | 41*4882a593Smuzhiyun #include <dt-bindings/clock/stm32mp1-clks.h> 42*4882a593Smuzhiyun hwspinlock@4c000000 { 43*4882a593Smuzhiyun compatible = "st,stm32-hwspinlock"; 44*4882a593Smuzhiyun #hwlock-cells = <1>; 45*4882a593Smuzhiyun reg = <0x4c000000 0x400>; 46*4882a593Smuzhiyun clocks = <&rcc HSEM>; 47*4882a593Smuzhiyun clock-names = "hsem"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun... 51