1*4882a593SmuzhiyunDevice tree configuration for the GFX display device on the ASPEED SoCs 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun - compatible 5*4882a593Smuzhiyun * Must be one of the following: 6*4882a593Smuzhiyun + aspeed,ast2500-gfx 7*4882a593Smuzhiyun + aspeed,ast2400-gfx 8*4882a593Smuzhiyun * In addition, the ASPEED pinctrl bindings require the 'syscon' property to 9*4882a593Smuzhiyun be present 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun - reg: Physical base address and length of the GFX registers 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun - interrupts: interrupt number for the GFX device 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun - clocks: clock number used to generate the pixel clock 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun - resets: reset line that must be released to use the GFX device 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun - memory-region: 20*4882a593Smuzhiyun Phandle to a memory region to allocate from, as defined in 21*4882a593Smuzhiyun Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyun 26*4882a593Smuzhiyungfx: display@1e6e6000 { 27*4882a593Smuzhiyun compatible = "aspeed,ast2500-gfx", "syscon"; 28*4882a593Smuzhiyun reg = <0x1e6e6000 0x1000>; 29*4882a593Smuzhiyun reg-io-width = <4>; 30*4882a593Smuzhiyun clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; 31*4882a593Smuzhiyun resets = <&syscon ASPEED_RESET_CRT1>; 32*4882a593Smuzhiyun interrupts = <0x19>; 33*4882a593Smuzhiyun memory-region = <&gfx_memory>; 34*4882a593Smuzhiyun}; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyungfx_memory: framebuffer { 37*4882a593Smuzhiyun size = <0x01000000>; 38*4882a593Smuzhiyun alignment = <0x01000000>; 39*4882a593Smuzhiyun compatible = "shared-dma-pool"; 40*4882a593Smuzhiyun reusable; 41*4882a593Smuzhiyun}; 42