xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/gpu/arm,mali-bifrost.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: ARM Mali Bifrost GPU
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Rob Herring <robh@kernel.org>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyunproperties:
13*4882a593Smuzhiyun  $nodename:
14*4882a593Smuzhiyun    pattern: '^gpu@[a-f0-9]+$'
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun  compatible:
17*4882a593Smuzhiyun    items:
18*4882a593Smuzhiyun      - enum:
19*4882a593Smuzhiyun          - amlogic,meson-g12a-mali
20*4882a593Smuzhiyun          - realtek,rtd1619-mali
21*4882a593Smuzhiyun          - rockchip,px30-mali
22*4882a593Smuzhiyun      - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun  reg:
25*4882a593Smuzhiyun    maxItems: 1
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun  interrupts:
28*4882a593Smuzhiyun    items:
29*4882a593Smuzhiyun      - description: Job interrupt
30*4882a593Smuzhiyun      - description: MMU interrupt
31*4882a593Smuzhiyun      - description: GPU interrupt
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun  interrupt-names:
34*4882a593Smuzhiyun    items:
35*4882a593Smuzhiyun      - const: job
36*4882a593Smuzhiyun      - const: mmu
37*4882a593Smuzhiyun      - const: gpu
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun  clocks:
40*4882a593Smuzhiyun    maxItems: 1
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun  mali-supply: true
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun  operating-points-v2: true
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun  power-domains:
47*4882a593Smuzhiyun    maxItems: 1
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun  resets:
50*4882a593Smuzhiyun    maxItems: 2
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun  "#cooling-cells":
53*4882a593Smuzhiyun    const: 2
54*4882a593Smuzhiyun
55*4882a593Smuzhiyunrequired:
56*4882a593Smuzhiyun  - compatible
57*4882a593Smuzhiyun  - reg
58*4882a593Smuzhiyun  - interrupts
59*4882a593Smuzhiyun  - interrupt-names
60*4882a593Smuzhiyun  - clocks
61*4882a593Smuzhiyun
62*4882a593SmuzhiyunadditionalProperties: false
63*4882a593Smuzhiyun
64*4882a593SmuzhiyunallOf:
65*4882a593Smuzhiyun  - if:
66*4882a593Smuzhiyun      properties:
67*4882a593Smuzhiyun        compatible:
68*4882a593Smuzhiyun          contains:
69*4882a593Smuzhiyun            const: amlogic,meson-g12a-mali
70*4882a593Smuzhiyun    then:
71*4882a593Smuzhiyun      required:
72*4882a593Smuzhiyun        - resets
73*4882a593Smuzhiyun
74*4882a593Smuzhiyunexamples:
75*4882a593Smuzhiyun  - |
76*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/irq.h>
77*4882a593Smuzhiyun    #include <dt-bindings/interrupt-controller/arm-gic.h>
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun    gpu@ffe40000 {
80*4882a593Smuzhiyun      compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
81*4882a593Smuzhiyun      reg = <0xffe40000 0x10000>;
82*4882a593Smuzhiyun      interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
83*4882a593Smuzhiyun             <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
84*4882a593Smuzhiyun             <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
85*4882a593Smuzhiyun      interrupt-names = "job", "mmu", "gpu";
86*4882a593Smuzhiyun      clocks = <&clk 1>;
87*4882a593Smuzhiyun      mali-supply = <&vdd_gpu>;
88*4882a593Smuzhiyun      operating-points-v2 = <&gpu_opp_table>;
89*4882a593Smuzhiyun      resets = <&reset 0>, <&reset 1>;
90*4882a593Smuzhiyun    };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun    gpu_opp_table: opp_table0 {
93*4882a593Smuzhiyun      compatible = "operating-points-v2";
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun      opp-533000000 {
96*4882a593Smuzhiyun        opp-hz = /bits/ 64 <533000000>;
97*4882a593Smuzhiyun        opp-microvolt = <1250000>;
98*4882a593Smuzhiyun      };
99*4882a593Smuzhiyun      opp-450000000 {
100*4882a593Smuzhiyun        opp-hz = /bits/ 64 <450000000>;
101*4882a593Smuzhiyun        opp-microvolt = <1150000>;
102*4882a593Smuzhiyun      };
103*4882a593Smuzhiyun      opp-400000000 {
104*4882a593Smuzhiyun        opp-hz = /bits/ 64 <400000000>;
105*4882a593Smuzhiyun        opp-microvolt = <1125000>;
106*4882a593Smuzhiyun      };
107*4882a593Smuzhiyun      opp-350000000 {
108*4882a593Smuzhiyun        opp-hz = /bits/ 64 <350000000>;
109*4882a593Smuzhiyun        opp-microvolt = <1075000>;
110*4882a593Smuzhiyun      };
111*4882a593Smuzhiyun      opp-266000000 {
112*4882a593Smuzhiyun        opp-hz = /bits/ 64 <266000000>;
113*4882a593Smuzhiyun        opp-microvolt = <1025000>;
114*4882a593Smuzhiyun      };
115*4882a593Smuzhiyun      opp-160000000 {
116*4882a593Smuzhiyun        opp-hz = /bits/ 64 <160000000>;
117*4882a593Smuzhiyun        opp-microvolt = <925000>;
118*4882a593Smuzhiyun      };
119*4882a593Smuzhiyun      opp-100000000 {
120*4882a593Smuzhiyun        opp-hz = /bits/ 64 <100000000>;
121*4882a593Smuzhiyun        opp-microvolt = <912500>;
122*4882a593Smuzhiyun      };
123*4882a593Smuzhiyun    };
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun...
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