1*4882a593SmuzhiyunZTE ZX296702 GPIO controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : "zte,zx296702-gpio" 5*4882a593Smuzhiyun- #gpio-cells : Should be two. The first cell is the pin number and the 6*4882a593Smuzhiyun second cell is used to specify optional parameters: 7*4882a593Smuzhiyun - bit 0 specifies polarity (0 for normal, 1 for inverted) 8*4882a593Smuzhiyun- gpio-controller : Marks the device node as a GPIO controller. 9*4882a593Smuzhiyun- interrupts : Interrupt mapping for GPIO IRQ. 10*4882a593Smuzhiyun- gpio-ranges : Interaction with the PINCTRL subsystem. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyungpio1: gpio@b008040 { 13*4882a593Smuzhiyun compatible = "zte,zx296702-gpio"; 14*4882a593Smuzhiyun reg = <0xb008040 0x40>; 15*4882a593Smuzhiyun gpio-controller; 16*4882a593Smuzhiyun #gpio-cells = <2>; 17*4882a593Smuzhiyun gpio-ranges = < &pmx0 0 54 2 &pmx0 2 59 14>; 18*4882a593Smuzhiyun interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 19*4882a593Smuzhiyun interrupt-parent = <&intc>; 20*4882a593Smuzhiyun interrupt-controller; 21*4882a593Smuzhiyun #interrupt-cells = <2>; 22*4882a593Smuzhiyun clock-names = "gpio_pclk"; 23*4882a593Smuzhiyun clocks = <&lsp0clk ZX296702_GPIO_CLK>; 24*4882a593Smuzhiyun}; 25