1*4882a593SmuzhiyunBindings for the Western Digital's MyBook Live memory-mapped GPIO controllers. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Western Digital MyBook Live has two memory-mapped GPIO controllers. 4*4882a593SmuzhiyunBoth GPIO controller only have a single 8-bit data register, where GPIO 5*4882a593Smuzhiyunstate can be read and/or written. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun - compatible: should be "wd,mbl-gpio" 9*4882a593Smuzhiyun - reg-names: must contain 10*4882a593Smuzhiyun "dat" - data register 11*4882a593Smuzhiyun - reg: address + size pairs describing the GPIO register sets; 12*4882a593Smuzhiyun order must correspond with the order of entries in reg-names 13*4882a593Smuzhiyun - #gpio-cells: must be set to 2. The first cell is the pin number and 14*4882a593Smuzhiyun the second cell is used to specify the gpio polarity: 15*4882a593Smuzhiyun 0 = active high 16*4882a593Smuzhiyun 1 = active low 17*4882a593Smuzhiyun - gpio-controller: Marks the device node as a gpio controller. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOptional properties: 20*4882a593Smuzhiyun - no-output: GPIOs are read-only. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExamples: 23*4882a593Smuzhiyun gpio0: gpio0@e0000000 { 24*4882a593Smuzhiyun compatible = "wd,mbl-gpio"; 25*4882a593Smuzhiyun reg-names = "dat"; 26*4882a593Smuzhiyun reg = <0xe0000000 0x1>; 27*4882a593Smuzhiyun #gpio-cells = <2>; 28*4882a593Smuzhiyun gpio-controller; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun gpio1: gpio1@e0100000 { 32*4882a593Smuzhiyun compatible = "wd,mbl-gpio"; 33*4882a593Smuzhiyun reg-names = "dat"; 34*4882a593Smuzhiyun reg = <0xe0100000 0x1>; 35*4882a593Smuzhiyun #gpio-cells = <2>; 36*4882a593Smuzhiyun gpio-controller; 37*4882a593Smuzhiyun no-output; 38*4882a593Smuzhiyun }; 39