xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2*4882a593Smuzhiyun%YAML 1.2
3*4882a593Smuzhiyun---
4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml#
5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml#
6*4882a593Smuzhiyun
7*4882a593Smuzhiyuntitle: UniPhier GPIO controller
8*4882a593Smuzhiyun
9*4882a593Smuzhiyunmaintainers:
10*4882a593Smuzhiyun  - Masahiro Yamada <yamada.masahiro@socionext.com>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyunproperties:
13*4882a593Smuzhiyun  $nodename:
14*4882a593Smuzhiyun    pattern: "^gpio@[0-9a-f]+$"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun  compatible:
17*4882a593Smuzhiyun    const: socionext,uniphier-gpio
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun  reg:
20*4882a593Smuzhiyun    maxItems: 1
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun  gpio-controller: true
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun  "#gpio-cells":
25*4882a593Smuzhiyun    const: 2
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun  interrupt-controller: true
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun  "#interrupt-cells":
30*4882a593Smuzhiyun    description: |
31*4882a593Smuzhiyun      The first cell defines the interrupt number.
32*4882a593Smuzhiyun      The second cell bits[3:0] is used to specify trigger type as follows:
33*4882a593Smuzhiyun        1 = low-to-high edge triggered
34*4882a593Smuzhiyun        2 = high-to-low edge triggered
35*4882a593Smuzhiyun        4 = active high level-sensitive
36*4882a593Smuzhiyun        8 = active low level-sensitive
37*4882a593Smuzhiyun      Valid combinations are 1, 2, 3, 4, 8.
38*4882a593Smuzhiyun    const: 2
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun  ngpios:
41*4882a593Smuzhiyun    minimum: 0
42*4882a593Smuzhiyun    maximum: 512
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun  gpio-ranges: true
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun  gpio-ranges-group-names:
47*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/string-array
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun  socionext,interrupt-ranges:
50*4882a593Smuzhiyun    description: |
51*4882a593Smuzhiyun      Specifies an interrupt number mapping between this GPIO controller and
52*4882a593Smuzhiyun      its interrupt parent, in the form of arbitrary number of
53*4882a593Smuzhiyun      <child-interrupt-base parent-interrupt-base length> triplets.
54*4882a593Smuzhiyun    $ref: /schemas/types.yaml#/definitions/uint32-matrix
55*4882a593Smuzhiyun
56*4882a593Smuzhiyunrequired:
57*4882a593Smuzhiyun  - compatible
58*4882a593Smuzhiyun  - reg
59*4882a593Smuzhiyun  - gpio-controller
60*4882a593Smuzhiyun  - "#gpio-cells"
61*4882a593Smuzhiyun  - interrupt-controller
62*4882a593Smuzhiyun  - "#interrupt-cells"
63*4882a593Smuzhiyun  - ngpios
64*4882a593Smuzhiyun  - gpio-ranges
65*4882a593Smuzhiyun  - socionext,interrupt-ranges
66*4882a593Smuzhiyun
67*4882a593SmuzhiyunadditionalProperties: false
68*4882a593Smuzhiyun
69*4882a593Smuzhiyunexamples:
70*4882a593Smuzhiyun  - |
71*4882a593Smuzhiyun    #include <dt-bindings/gpio/gpio.h>
72*4882a593Smuzhiyun    #include <dt-bindings/gpio/uniphier-gpio.h>
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun    gpio: gpio@55000000 {
75*4882a593Smuzhiyun        compatible = "socionext,uniphier-gpio";
76*4882a593Smuzhiyun        reg = <0x55000000 0x200>;
77*4882a593Smuzhiyun        interrupt-parent = <&aidet>;
78*4882a593Smuzhiyun        interrupt-controller;
79*4882a593Smuzhiyun        #interrupt-cells = <2>;
80*4882a593Smuzhiyun        gpio-controller;
81*4882a593Smuzhiyun        #gpio-cells = <2>;
82*4882a593Smuzhiyun        gpio-ranges = <&pinctrl 0 0 0>;
83*4882a593Smuzhiyun        gpio-ranges-group-names = "gpio_range";
84*4882a593Smuzhiyun        ngpios = <248>;
85*4882a593Smuzhiyun        socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>;
86*4882a593Smuzhiyun    };
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun    // Consumer:
89*4882a593Smuzhiyun    // Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC
90*4882a593Smuzhiyun    // document. Unfortunately, only the one's place is octal in the port
91*4882a593Smuzhiyun    // numbering. (That is, PORT 8, 9, 18, 19, 28, 29, ... do not exist.)
92*4882a593Smuzhiyun    // UNIPHIER_GPIO_PORT() is a helper macro to calculate 29 * 8 + 4.
93*4882a593Smuzhiyun    sdhci0_pwrseq {
94*4882a593Smuzhiyun        compatible = "mmc-pwrseq-emmc";
95*4882a593Smuzhiyun        reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>;
96*4882a593Smuzhiyun    };
97