1*4882a593SmuzhiyunRockchip RK3328 GRF (General Register Files) GPIO controller. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunIn Rockchip RK3328, the output only GPIO_MUTE pin, originally for codec mute 4*4882a593Smuzhiyuncontrol, can also be used for general purpose. It is manipulated by the 5*4882a593SmuzhiyunGRF_SOC_CON10 register in GRF. Aside from the GPIO_MUTE pin, the HDMI pins can 6*4882a593Smuzhiyunalso be set in the same way. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunCurrently this GPIO controller only supports the mute pin. If needed in the 9*4882a593Smuzhiyunfuture, the HDMI pins support can also be added. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties: 12*4882a593Smuzhiyun- compatible: Should contain "rockchip,rk3328-grf-gpio". 13*4882a593Smuzhiyun- gpio-controller: Marks the device node as a gpio controller. 14*4882a593Smuzhiyun- #gpio-cells: Should be 2. The first cell is the pin number and 15*4882a593Smuzhiyun the second cell is used to specify the gpio polarity: 16*4882a593Smuzhiyun 0 = Active high, 17*4882a593Smuzhiyun 1 = Active low. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun grf: syscon@ff100000 { 22*4882a593Smuzhiyun compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd"; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun grf_gpio: grf-gpio { 25*4882a593Smuzhiyun compatible = "rockchip,rk3328-grf-gpio"; 26*4882a593Smuzhiyun gpio-controller; 27*4882a593Smuzhiyun #gpio-cells = <2>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunNote: The grf_gpio node should be declared as the child of the GRF (General 32*4882a593SmuzhiyunRegister File) node. The GPIO_MUTE pin is referred to as <&grf_gpio 0>. 33