1*4882a593SmuzhiyunBindings for the National Instruments 169445 GPIO NAND controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe 169445 GPIO NAND controller has two memory mapped GPIO registers, one 4*4882a593Smuzhiyunfor input (the ready signal) and one for output (control signals). It is 5*4882a593Smuzhiyunintended to be used with the GPIO NAND driver. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun - compatible: should be "ni,169445-nand-gpio" 9*4882a593Smuzhiyun - reg-names: must contain 10*4882a593Smuzhiyun "dat" - data register 11*4882a593Smuzhiyun - reg: address + size pairs describing the GPIO register sets; 12*4882a593Smuzhiyun order must correspond with the order of entries in reg-names 13*4882a593Smuzhiyun - #gpio-cells: must be set to 2. The first cell is the pin number and 14*4882a593Smuzhiyun the second cell is used to specify the gpio polarity: 15*4882a593Smuzhiyun 0 = active high 16*4882a593Smuzhiyun 1 = active low 17*4882a593Smuzhiyun - gpio-controller: Marks the device node as a gpio controller. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOptional properties: 20*4882a593Smuzhiyun - no-output: disables driving output on the pins 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExamples: 23*4882a593Smuzhiyun gpio1: nand-gpio-out@1f300010 { 24*4882a593Smuzhiyun compatible = "ni,169445-nand-gpio"; 25*4882a593Smuzhiyun reg = <0x1f300010 0x4>; 26*4882a593Smuzhiyun reg-names = "dat"; 27*4882a593Smuzhiyun gpio-controller; 28*4882a593Smuzhiyun #gpio-cells = <2>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun gpio2: nand-gpio-in@1f300014 { 32*4882a593Smuzhiyun compatible = "ni,169445-nand-gpio"; 33*4882a593Smuzhiyun reg = <0x1f300014 0x4>; 34*4882a593Smuzhiyun reg-names = "dat"; 35*4882a593Smuzhiyun gpio-controller; 36*4882a593Smuzhiyun #gpio-cells = <2>; 37*4882a593Smuzhiyun no-output; 38*4882a593Smuzhiyun }; 39