1*4882a593SmuzhiyunMediatek MT7621 SoC GPIO controller bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe IP core used inside these SoCs has 3 banks of 32 GPIOs each. 4*4882a593SmuzhiyunThe registers of all the banks are interwoven inside one single IO range. 5*4882a593SmuzhiyunWe load one GPIO controller instance per bank. Also the GPIO controller can receive 6*4882a593Smuzhiyuninterrupts on any of the GPIOs, either edge or level. It then interrupts the CPU 7*4882a593Smuzhiyunusing GIC INT12. 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties for the top level node: 10*4882a593Smuzhiyun- #gpio-cells : Should be two. The first cell is the GPIO pin number and the 11*4882a593Smuzhiyun second cell specifies GPIO flags, as defined in <dt-bindings/gpio/gpio.h>. 12*4882a593Smuzhiyun Only the GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. 13*4882a593Smuzhiyun- #interrupt-cells : Specifies the number of cells needed to encode an 14*4882a593Smuzhiyun interrupt. Should be 2. The first cell defines the interrupt number, 15*4882a593Smuzhiyun the second encodes the trigger flags encoded as described in 16*4882a593Smuzhiyun Documentation/devicetree/bindings/interrupt-controller/interrupts.txt 17*4882a593Smuzhiyun- compatible: 18*4882a593Smuzhiyun - "mediatek,mt7621-gpio" for Mediatek controllers 19*4882a593Smuzhiyun- reg : Physical base address and length of the controller's registers 20*4882a593Smuzhiyun- interrupt-parent : phandle of the parent interrupt controller. 21*4882a593Smuzhiyun- interrupts : Interrupt specifier for the controllers interrupt. 22*4882a593Smuzhiyun- interrupt-controller : Mark the device node as an interrupt controller. 23*4882a593Smuzhiyun- gpio-controller : Marks the device node as a GPIO controller. 24*4882a593Smuzhiyun 25*4882a593SmuzhiyunExample: 26*4882a593Smuzhiyun gpio@600 { 27*4882a593Smuzhiyun #gpio-cells = <2>; 28*4882a593Smuzhiyun #interrupt-cells = <2>; 29*4882a593Smuzhiyun compatible = "mediatek,mt7621-gpio"; 30*4882a593Smuzhiyun gpio-controller; 31*4882a593Smuzhiyun interrupt-controller; 32*4882a593Smuzhiyun reg = <0x600 0x100>; 33*4882a593Smuzhiyun interrupt-parent = <&gic>; 34*4882a593Smuzhiyun interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>; 35*4882a593Smuzhiyun }; 36