1*4882a593SmuzhiyunIntel IXP4xx XScale Networking Processors GPIO 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis GPIO controller is found in the Intel IXP4xx processors. 4*4882a593SmuzhiyunIt supports 16 GPIO lines. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThe interrupt portions of the GPIO controller is hierarchical: 7*4882a593Smuzhiyunthe synchronous edge detector is part of the GPIO block, but the 8*4882a593Smuzhiyunactual enabling/disabling of the interrupt line is done in the 9*4882a593Smuzhiyunmain IXP4xx interrupt controller which has a 1:1 mapping for 10*4882a593Smuzhiyunthe first 12 GPIO lines to 12 system interrupts. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunThe remaining 4 GPIO lines can not be used for receiving 13*4882a593Smuzhiyuninterrupts. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunThe interrupt parent of this GPIO controller must be the 16*4882a593SmuzhiyunIXP4xx interrupt controller. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunRequired properties: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- compatible : Should be 21*4882a593Smuzhiyun "intel,ixp4xx-gpio" 22*4882a593Smuzhiyun- reg : Should contain registers location and length 23*4882a593Smuzhiyun- gpio-controller : marks this as a GPIO controller 24*4882a593Smuzhiyun- #gpio-cells : Should be 2, see gpio/gpio.txt 25*4882a593Smuzhiyun- interrupt-controller : marks this as an interrupt controller 26*4882a593Smuzhiyun- #interrupt-cells : a standard two-cell interrupt, see 27*4882a593Smuzhiyun interrupt-controller/interrupts.txt 28*4882a593Smuzhiyun 29*4882a593SmuzhiyunExample: 30*4882a593Smuzhiyun 31*4882a593Smuzhiyungpio0: gpio@c8004000 { 32*4882a593Smuzhiyun compatible = "intel,ixp4xx-gpio"; 33*4882a593Smuzhiyun reg = <0xc8004000 0x1000>; 34*4882a593Smuzhiyun gpio-controller; 35*4882a593Smuzhiyun #gpio-cells = <2>; 36*4882a593Smuzhiyun interrupt-controller; 37*4882a593Smuzhiyun #interrupt-cells = <2>; 38*4882a593Smuzhiyun}; 39