1*4882a593Smuzhiyun* IBM/AMCC/APM GPIO Controller for PowerPC 4XX series and compatible SoCs 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunAll GPIOs are pin-shared with other functions. DCRs control whether a 4*4882a593Smuzhiyunparticular pin that has GPIO capabilities acts as a GPIO or is used for 5*4882a593Smuzhiyunanother purpose. GPIO outputs are separately programmable to emulate 6*4882a593Smuzhiyunan open-drain driver. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun - compatible: must be "ibm,ppc4xx-gpio" 10*4882a593Smuzhiyun - reg: address and length of the register set for the device 11*4882a593Smuzhiyun - #gpio-cells: must be set to 2. The first cell is the pin number 12*4882a593Smuzhiyun and the second cell is used to specify the gpio polarity: 13*4882a593Smuzhiyun 0 = active high 14*4882a593Smuzhiyun 1 = active low 15*4882a593Smuzhiyun - gpio-controller: marks the device node as a gpio controller. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunExample: 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunGPIO0: gpio@ef600b00 { 20*4882a593Smuzhiyun compatible = "ibm,ppc4xx-gpio"; 21*4882a593Smuzhiyun reg = <0xef600b00 0x00000048>; 22*4882a593Smuzhiyun #gpio-cells = <2>; 23*4882a593Smuzhiyun gpio-controller; 24*4882a593Smuzhiyun}; 25