1*4882a593SmuzhiyunNXP LPC32xx SoC GPIO controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: must be "nxp,lpc3220-gpio" 5*4882a593Smuzhiyun- reg: Physical base address and length of the controller's registers. 6*4882a593Smuzhiyun- gpio-controller: Marks the device node as a GPIO controller. 7*4882a593Smuzhiyun- #gpio-cells: Should be 3: 8*4882a593Smuzhiyun 1) bank: 9*4882a593Smuzhiyun 0: GPIO P0 10*4882a593Smuzhiyun 1: GPIO P1 11*4882a593Smuzhiyun 2: GPIO P2 12*4882a593Smuzhiyun 3: GPIO P3 13*4882a593Smuzhiyun 4: GPI P3 14*4882a593Smuzhiyun 5: GPO P3 15*4882a593Smuzhiyun 2) pin number 16*4882a593Smuzhiyun 3) optional parameters: 17*4882a593Smuzhiyun - bit 0 specifies polarity (0 for normal, 1 for inverted) 18*4882a593Smuzhiyun- reg: Index of the GPIO group 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunExample: 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun gpio: gpio@40028000 { 23*4882a593Smuzhiyun compatible = "nxp,lpc3220-gpio"; 24*4882a593Smuzhiyun reg = <0x40028000 0x1000>; 25*4882a593Smuzhiyun gpio-controller; 26*4882a593Smuzhiyun #gpio-cells = <3>; /* bank, pin, flags */ 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun leds { 30*4882a593Smuzhiyun compatible = "gpio-leds"; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun led0 { 33*4882a593Smuzhiyun gpios = <&gpio 5 1 1>; /* GPO_P3 1, active low */ 34*4882a593Smuzhiyun linux,default-trigger = "heartbeat"; 35*4882a593Smuzhiyun default-state = "off"; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun led1 { 39*4882a593Smuzhiyun gpios = <&gpio 5 14 1>; /* GPO_P3 14, active low */ 40*4882a593Smuzhiyun linux,default-trigger = "timer"; 41*4882a593Smuzhiyun default-state = "off"; 42*4882a593Smuzhiyun }; 43*4882a593Smuzhiyun }; 44