1*4882a593SmuzhiyunXilinx plb/axi GPIO controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunDual channel GPIO controller with configurable number of pins 4*4882a593Smuzhiyun(from 1 to 32 per channel). Every pin can be configured as 5*4882a593Smuzhiyuninput/output/tristate. Both channels share the same global IRQ but 6*4882a593Smuzhiyunlocal interrupts can be enabled on channel basis. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun- compatible : Should be "xlnx,xps-gpio-1.00.a" 10*4882a593Smuzhiyun- reg : Address and length of the register set for the device 11*4882a593Smuzhiyun- #gpio-cells : Should be two. The first cell is the pin number and the 12*4882a593Smuzhiyun second cell is used to specify optional parameters (currently unused). 13*4882a593Smuzhiyun- gpio-controller : Marks the device node as a GPIO controller. 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun- interrupts : Interrupt mapping for GPIO IRQ. 17*4882a593Smuzhiyun- xlnx,all-inputs : if n-th bit is setup, GPIO-n is input 18*4882a593Smuzhiyun- xlnx,dout-default : if n-th bit is 1, GPIO-n default value is 1 19*4882a593Smuzhiyun- xlnx,gpio-width : gpio width 20*4882a593Smuzhiyun- xlnx,tri-default : if n-th bit is 1, GPIO-n is in tristate mode 21*4882a593Smuzhiyun- xlnx,is-dual : if 1, controller also uses the second channel 22*4882a593Smuzhiyun- xlnx,all-inputs-2 : as above but for the second channel 23*4882a593Smuzhiyun- xlnx,dout-default-2 : as above but the second channel 24*4882a593Smuzhiyun- xlnx,gpio2-width : as above but for the second channel 25*4882a593Smuzhiyun- xlnx,tri-default-2 : as above but for the second channel 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample: 29*4882a593Smuzhiyungpio: gpio@40000000 { 30*4882a593Smuzhiyun #gpio-cells = <2>; 31*4882a593Smuzhiyun compatible = "xlnx,xps-gpio-1.00.a"; 32*4882a593Smuzhiyun gpio-controller ; 33*4882a593Smuzhiyun interrupt-parent = <µblaze_0_intc>; 34*4882a593Smuzhiyun interrupts = < 6 2 >; 35*4882a593Smuzhiyun reg = < 0x40000000 0x10000 >; 36*4882a593Smuzhiyun xlnx,all-inputs = <0x0>; 37*4882a593Smuzhiyun xlnx,all-inputs-2 = <0x0>; 38*4882a593Smuzhiyun xlnx,dout-default = <0x0>; 39*4882a593Smuzhiyun xlnx,dout-default-2 = <0x0>; 40*4882a593Smuzhiyun xlnx,gpio-width = <0x2>; 41*4882a593Smuzhiyun xlnx,gpio2-width = <0x2>; 42*4882a593Smuzhiyun xlnx,interrupt-present = <0x1>; 43*4882a593Smuzhiyun xlnx,is-dual = <0x1>; 44*4882a593Smuzhiyun xlnx,tri-default = <0xffffffff>; 45*4882a593Smuzhiyun xlnx,tri-default-2 = <0xffffffff>; 46*4882a593Smuzhiyun} ; 47