1*4882a593SmuzhiyunAPM X-Gene SoC GPIO controller bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis is a gpio controller that is part of the flash controller. 4*4882a593SmuzhiyunThis gpio controller controls a total of 48 gpios. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunRequired properties: 7*4882a593Smuzhiyun- compatible: "apm,xgene-gpio" for X-Gene GPIO controller 8*4882a593Smuzhiyun- reg: Physical base address and size of the controller's registers 9*4882a593Smuzhiyun- #gpio-cells: Should be two. 10*4882a593Smuzhiyun - first cell is the pin number 11*4882a593Smuzhiyun - second cell is used to specify the gpio polarity: 12*4882a593Smuzhiyun 0 = active high 13*4882a593Smuzhiyun 1 = active low 14*4882a593Smuzhiyun- gpio-controller: Marks the device node as a GPIO controller. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunExample: 17*4882a593Smuzhiyun gpio0: gpio0@1701c000 { 18*4882a593Smuzhiyun compatible = "apm,xgene-gpio"; 19*4882a593Smuzhiyun reg = <0x0 0x1701c000 0x0 0x40>; 20*4882a593Smuzhiyun gpio-controller; 21*4882a593Smuzhiyun #gpio-cells = <2>; 22*4882a593Smuzhiyun }; 23