1*4882a593SmuzhiyunAPM X-Gene Standby GPIO controller bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis is a gpio controller in the standby domain. It also supports interrupt in 4*4882a593Smuzhiyunsome particular pins which are sourced to its parent interrupt controller 5*4882a593Smuzhiyunas diagram below: 6*4882a593Smuzhiyun +-----------------+ 7*4882a593Smuzhiyun | X-Gene standby | 8*4882a593Smuzhiyun | GPIO controller +------ GPIO_0 9*4882a593Smuzhiyun+------------+ | | ... 10*4882a593Smuzhiyun| Parent IRQ | EXT_INT_0 | +------ GPIO_8/EXT_INT_0 11*4882a593Smuzhiyun| controller | (SPI40) | | ... 12*4882a593Smuzhiyun| (GICv2) +--------------+ +------ GPIO_[N+8]/EXT_INT_N 13*4882a593Smuzhiyun| | ... | | 14*4882a593Smuzhiyun| | EXT_INT_N | +------ GPIO_[N+9] 15*4882a593Smuzhiyun| | (SPI[40 + N])| | ... 16*4882a593Smuzhiyun| +--------------+ +------ GPIO_MAX 17*4882a593Smuzhiyun+------------+ +-----------------+ 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunRequired properties: 20*4882a593Smuzhiyun- compatible: "apm,xgene-gpio-sb" for the X-Gene Standby GPIO controller 21*4882a593Smuzhiyun- reg: Physical base address and size of the controller's registers 22*4882a593Smuzhiyun- #gpio-cells: Should be two. 23*4882a593Smuzhiyun - first cell is the pin number 24*4882a593Smuzhiyun - second cell is used to specify the gpio polarity: 25*4882a593Smuzhiyun 0 = active high 26*4882a593Smuzhiyun 1 = active low 27*4882a593Smuzhiyun- gpio-controller: Marks the device node as a GPIO controller. 28*4882a593Smuzhiyun- interrupts: The EXT_INT_0 parent interrupt resource must be listed first. 29*4882a593Smuzhiyun- interrupt-cells: Should be two. 30*4882a593Smuzhiyun - first cell is 0-N coresponding for EXT_INT_0 to EXT_INT_N. 31*4882a593Smuzhiyun - second cell is used to specify flags. 32*4882a593Smuzhiyun- interrupt-controller: Marks the device node as an interrupt controller. 33*4882a593Smuzhiyun- apm,nr-gpios: Optional, specify number of gpios pin. 34*4882a593Smuzhiyun- apm,nr-irqs: Optional, specify number of interrupt pins. 35*4882a593Smuzhiyun- apm,irq-start: Optional, specify lowest gpio pin support interrupt. 36*4882a593Smuzhiyun 37*4882a593SmuzhiyunExample: 38*4882a593Smuzhiyun sbgpio: gpio@17001000{ 39*4882a593Smuzhiyun compatible = "apm,xgene-gpio-sb"; 40*4882a593Smuzhiyun reg = <0x0 0x17001000 0x0 0x400>; 41*4882a593Smuzhiyun #gpio-cells = <2>; 42*4882a593Smuzhiyun gpio-controller; 43*4882a593Smuzhiyun interrupts = <0x0 0x28 0x1>, 44*4882a593Smuzhiyun <0x0 0x29 0x1>, 45*4882a593Smuzhiyun <0x0 0x2a 0x1>, 46*4882a593Smuzhiyun <0x0 0x2b 0x1>, 47*4882a593Smuzhiyun <0x0 0x2c 0x1>, 48*4882a593Smuzhiyun <0x0 0x2d 0x1>; 49*4882a593Smuzhiyun interrupt-parent = <&gic>; 50*4882a593Smuzhiyun #interrupt-cells = <2>; 51*4882a593Smuzhiyun interrupt-controller; 52*4882a593Smuzhiyun apm,nr-gpios = <22>; 53*4882a593Smuzhiyun apm,nr-irqs = <6>; 54*4882a593Smuzhiyun apm,irq-start = <8>; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun testuser { 58*4882a593Smuzhiyun compatible = "example,testuser"; 59*4882a593Smuzhiyun /* Use the GPIO_13/EXT_INT_5 line as an active high triggered 60*4882a593Smuzhiyun * level interrupt 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun interrupts = <5 4>; 63*4882a593Smuzhiyun interrupt-parent = <&sbgpio>; 64*4882a593Smuzhiyun }; 65