1*4882a593SmuzhiyunLantiq SoC Serial To Parallel (STP) GPIO controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Serial To Parallel (STP) is found on MIPS based Lantiq socs. It is a 4*4882a593Smuzhiyunperipheral controller used to drive external shift register cascades. At most 5*4882a593Smuzhiyun3 groups of 8 bits can be driven. The hardware is able to allow the DSL modem 6*4882a593Smuzhiyunto drive the 2 LSBs of the cascade automatically. 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunRequired properties: 10*4882a593Smuzhiyun- compatible : Should be "lantiq,gpio-stp-xway" 11*4882a593Smuzhiyun- reg : Address and length of the register set for the device 12*4882a593Smuzhiyun- #gpio-cells : Should be two. The first cell is the pin number and 13*4882a593Smuzhiyun the second cell is used to specify optional parameters (currently 14*4882a593Smuzhiyun unused). 15*4882a593Smuzhiyun- gpio-controller : Marks the device node as a gpio controller. 16*4882a593Smuzhiyun 17*4882a593SmuzhiyunOptional properties: 18*4882a593Smuzhiyun- lantiq,shadow : The default value that we shall assume as already set on the 19*4882a593Smuzhiyun shift register cascade. 20*4882a593Smuzhiyun- lantiq,groups : Set the 3 bit mask to select which of the 3 groups are enabled 21*4882a593Smuzhiyun in the shift register cascade. 22*4882a593Smuzhiyun- lantiq,dsl : The dsl core can control the 2 LSBs of the gpio cascade. This 2 bit 23*4882a593Smuzhiyun property can enable this feature. 24*4882a593Smuzhiyun- lantiq,phy1 : The gphy1 core can control 3 bits of the gpio cascade. 25*4882a593Smuzhiyun- lantiq,phy2 : The gphy2 core can control 3 bits of the gpio cascade. 26*4882a593Smuzhiyun- lantiq,rising : use rising instead of falling edge for the shift register 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyungpio1: stp@e100bb0 { 31*4882a593Smuzhiyun compatible = "lantiq,gpio-stp-xway"; 32*4882a593Smuzhiyun reg = <0xE100BB0 0x40>; 33*4882a593Smuzhiyun #gpio-cells = <2>; 34*4882a593Smuzhiyun gpio-controller; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun lantiq,shadow = <0xffff>; 37*4882a593Smuzhiyun lantiq,groups = <0x7>; 38*4882a593Smuzhiyun lantiq,dsl = <0x3>; 39*4882a593Smuzhiyun lantiq,phy1 = <0x7>; 40*4882a593Smuzhiyun lantiq,phy2 = <0x7>; 41*4882a593Smuzhiyun /* lantiq,rising; */ 42*4882a593Smuzhiyun}; 43