1*4882a593SmuzhiyunSpreadtrum GPIO controller bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe controller's registers are organized as sets of sixteen 16-bit 4*4882a593Smuzhiyunregisters with each set controlling a bank of up to 16 pins. A single 5*4882a593Smuzhiyuninterrupt is shared for all of the banks handled by the controller. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun- compatible: Should be "sprd,sc9860-gpio". 9*4882a593Smuzhiyun- reg: Define the base and range of the I/O address space containing 10*4882a593Smuzhiyunthe GPIO controller registers. 11*4882a593Smuzhiyun- gpio-controller: Marks the device node as a GPIO controller. 12*4882a593Smuzhiyun- #gpio-cells: Should be <2>. The first cell is the gpio number and 13*4882a593Smuzhiyunthe second cell is used to specify optional parameters. 14*4882a593Smuzhiyun- interrupt-controller: Marks the device node as an interrupt controller. 15*4882a593Smuzhiyun- #interrupt-cells: Should be <2>. Specifies the number of cells needed 16*4882a593Smuzhiyunto encode interrupt source. 17*4882a593Smuzhiyun- interrupts: Should be the port interrupt shared by all the gpios. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample: 20*4882a593Smuzhiyun ap_gpio: gpio@40280000 { 21*4882a593Smuzhiyun compatible = "sprd,sc9860-gpio"; 22*4882a593Smuzhiyun reg = <0 0x40280000 0 0x1000>; 23*4882a593Smuzhiyun gpio-controller; 24*4882a593Smuzhiyun #gpio-cells = <2>; 25*4882a593Smuzhiyun interrupt-controller; 26*4882a593Smuzhiyun #interrupt-cells = <2>; 27*4882a593Smuzhiyun interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 28*4882a593Smuzhiyun }; 29