1*4882a593Smuzhiyun* Marvell EBU GPIO controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio", 6*4882a593Smuzhiyun "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio". 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove, 9*4882a593Smuzhiyun Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio" 10*4882a593Smuzhiyun should be used for the Discovery MV78200. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun "marvel,armadaxp-gpio" should be used for all Armada XP SoCs 13*4882a593Smuzhiyun (MV78230, MV78260, MV78460). 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K 16*4882a593Smuzhiyun SoCs (either from AP or CP), see 17*4882a593Smuzhiyun Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt 18*4882a593Smuzhiyun for specific details about the offset property. 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- reg: Address and length of the register set for the device. Only one 21*4882a593Smuzhiyun entry is expected, except for the "marvell,armadaxp-gpio" variant 22*4882a593Smuzhiyun for which two entries are expected: one for the general registers, 23*4882a593Smuzhiyun one for the per-cpu registers. Not used for marvell,armada-8k-gpio. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun- interrupts: The list of interrupts that are used for all the pins 26*4882a593Smuzhiyun managed by this GPIO bank. There can be more than one interrupt 27*4882a593Smuzhiyun (example: 1 interrupt per 8 pins on Armada XP, which means 4 28*4882a593Smuzhiyun interrupts per bank of 32 GPIOs). 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun- interrupt-controller: identifies the node as an interrupt controller 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun- #interrupt-cells: specifies the number of cells needed to encode an 33*4882a593Smuzhiyun interrupt source. Should be two. 34*4882a593Smuzhiyun The first cell is the GPIO number. 35*4882a593Smuzhiyun The second cell is used to specify flags: 36*4882a593Smuzhiyun bits[3:0] trigger type and level flags: 37*4882a593Smuzhiyun 1 = low-to-high edge triggered. 38*4882a593Smuzhiyun 2 = high-to-low edge triggered. 39*4882a593Smuzhiyun 4 = active high level-sensitive. 40*4882a593Smuzhiyun 8 = active low level-sensitive. 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun- gpio-controller: marks the device node as a gpio controller 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun- ngpios: number of GPIOs this controller has 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun- #gpio-cells: Should be two. The first cell is the pin number. The 47*4882a593Smuzhiyun second cell is reserved for flags, unused at the moment. 48*4882a593Smuzhiyun 49*4882a593SmuzhiyunOptional properties: 50*4882a593Smuzhiyun 51*4882a593SmuzhiyunIn order to use the GPIO lines in PWM mode, some additional optional 52*4882a593Smuzhiyunproperties are required. 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun- compatible: Must contain "marvell,armada-370-gpio" 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun- reg: an additional register set is needed, for the GPIO Blink 57*4882a593Smuzhiyun Counter on/off registers. 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun- reg-names: Must contain an entry "pwm" corresponding to the 60*4882a593Smuzhiyun additional register range needed for PWM operation. 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun- #pwm-cells: Should be two. The first cell is the GPIO line number. The 63*4882a593Smuzhiyun second cell is the period in nanoseconds. 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun- clocks: Must be a phandle to the clock for the GPIO controller. 66*4882a593Smuzhiyun 67*4882a593SmuzhiyunExample: 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun gpio0: gpio@d0018100 { 70*4882a593Smuzhiyun compatible = "marvell,armadaxp-gpio"; 71*4882a593Smuzhiyun reg = <0xd0018100 0x40>, 72*4882a593Smuzhiyun <0xd0018800 0x30>; 73*4882a593Smuzhiyun ngpios = <32>; 74*4882a593Smuzhiyun gpio-controller; 75*4882a593Smuzhiyun #gpio-cells = <2>; 76*4882a593Smuzhiyun interrupt-controller; 77*4882a593Smuzhiyun #interrupt-cells = <2>; 78*4882a593Smuzhiyun interrupts = <16>, <17>, <18>, <19>; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun gpio1: gpio@18140 { 82*4882a593Smuzhiyun compatible = "marvell,armada-370-gpio"; 83*4882a593Smuzhiyun reg = <0x18140 0x40>, <0x181c8 0x08>; 84*4882a593Smuzhiyun reg-names = "gpio", "pwm"; 85*4882a593Smuzhiyun ngpios = <17>; 86*4882a593Smuzhiyun gpio-controller; 87*4882a593Smuzhiyun #gpio-cells = <2>; 88*4882a593Smuzhiyun #pwm-cells = <2>; 89*4882a593Smuzhiyun interrupt-controller; 90*4882a593Smuzhiyun #interrupt-cells = <2>; 91*4882a593Smuzhiyun interrupts = <87>, <88>, <89>; 92*4882a593Smuzhiyun clocks = <&coreclk 0>; 93*4882a593Smuzhiyun }; 94