1*4882a593Smuzhiyun* Freescale MPC512x/MPC8xxx/QorIQ/Layerscape GPIO controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : Should be "fsl,<soc>-gpio" 5*4882a593Smuzhiyun The following <soc>s are known to be supported: 6*4882a593Smuzhiyun mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq, 7*4882a593Smuzhiyun ls1021a, ls1043a, ls2080a, ls1028a, ls1088a. 8*4882a593Smuzhiyun- reg : Address and length of the register set for the device 9*4882a593Smuzhiyun- interrupts : Should be the port interrupt shared by all 32 pins. 10*4882a593Smuzhiyun- #gpio-cells : Should be two. The first cell is the pin number and 11*4882a593Smuzhiyun the second cell is used to specify the gpio polarity: 12*4882a593Smuzhiyun 0 = active high 13*4882a593Smuzhiyun 1 = active low 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun- little-endian : GPIO registers are used as little endian. If not 17*4882a593Smuzhiyun present registers are used as big endian by default. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample of gpio-controller node for a mpc5125 SoC: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyungpio0: gpio@1100 { 22*4882a593Smuzhiyun compatible = "fsl,mpc5125-gpio"; 23*4882a593Smuzhiyun #gpio-cells = <2>; 24*4882a593Smuzhiyun reg = <0x1100 0x080>; 25*4882a593Smuzhiyun interrupts = <78 0x8>; 26*4882a593Smuzhiyun}; 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunExample of gpio-controller node for a ls2080a SoC: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyungpio0: gpio@2300000 { 31*4882a593Smuzhiyun compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; 32*4882a593Smuzhiyun reg = <0x0 0x2300000 0x0 0x10000>; 33*4882a593Smuzhiyun interrupts = <0 36 0x4>; /* Level high type */ 34*4882a593Smuzhiyun gpio-controller; 35*4882a593Smuzhiyun little-endian; 36*4882a593Smuzhiyun #gpio-cells = <2>; 37*4882a593Smuzhiyun interrupt-controller; 38*4882a593Smuzhiyun #interrupt-cells = <2>; 39*4882a593Smuzhiyun}; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunExample of gpio-controller node for a ls1028a/ls1088a SoC: 43*4882a593Smuzhiyun 44*4882a593Smuzhiyungpio1: gpio@2300000 { 45*4882a593Smuzhiyun compatible = "fsl,ls1028a-gpio", "fsl,ls1088a-gpio", "fsl,qoriq-gpio"; 46*4882a593Smuzhiyun reg = <0x0 0x2300000 0x0 0x10000>; 47*4882a593Smuzhiyun interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 48*4882a593Smuzhiyun gpio-controller; 49*4882a593Smuzhiyun #gpio-cells = <2>; 50*4882a593Smuzhiyun interrupt-controller; 51*4882a593Smuzhiyun #interrupt-cells = <2>; 52*4882a593Smuzhiyun little-endian; 53*4882a593Smuzhiyun}; 54