1*4882a593SmuzhiyunLantiq SoC External Bus memory mapped GPIO controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunBy attaching hardware latches to the EBU it is possible to create output 4*4882a593Smuzhiyunonly gpios. This driver configures a special memory address, which when 5*4882a593Smuzhiyunwritten to outputs 16 bit to the latches. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunThe node describing the memory mapped GPIOs needs to be a child of the node 8*4882a593Smuzhiyundescribing the "lantiq,localbus". 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible : Should be "lantiq,gpio-mm-lantiq" 12*4882a593Smuzhiyun- reg : Address and length of the register set for the device 13*4882a593Smuzhiyun- #gpio-cells : Should be two. The first cell is the pin number and 14*4882a593Smuzhiyun the second cell is used to specify optional parameters (currently 15*4882a593Smuzhiyun unused). 16*4882a593Smuzhiyun- gpio-controller : Marks the device node as a gpio controller. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun- lantiq,shadow : The default value that we shall assume as already set on the 20*4882a593Smuzhiyun shift register cascade. 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunlocalbus@0 { 25*4882a593Smuzhiyun #address-cells = <2>; 26*4882a593Smuzhiyun #size-cells = <1>; 27*4882a593Smuzhiyun ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ 28*4882a593Smuzhiyun 1 0 0x4000000 0x4000010>; /* addsel1 */ 29*4882a593Smuzhiyun compatible = "lantiq,localbus", "simple-bus"; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun gpio_mm0: gpio@4000000 { 32*4882a593Smuzhiyun compatible = "lantiq,gpio-mm"; 33*4882a593Smuzhiyun reg = <1 0x0 0x10>; 34*4882a593Smuzhiyun gpio-controller; 35*4882a593Smuzhiyun #gpio-cells = <2>; 36*4882a593Smuzhiyun lantiq,shadow = <0x77f> 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun} 39