1*4882a593SmuzhiyunSpreadtrum EIC controller bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe EIC is the abbreviation of external interrupt controller, which can 4*4882a593Smuzhiyunbe used only in input mode. The Spreadtrum platform has 2 EIC controllers, 5*4882a593Smuzhiyunone is in digital chip, and another one is in PMIC. The digital chip EIC 6*4882a593Smuzhiyuncontroller contains 4 sub-modules: EIC-debounce, EIC-latch, EIC-async and 7*4882a593SmuzhiyunEIC-sync. But the PMIC EIC controller contains only one EIC-debounce sub- 8*4882a593Smuzhiyunmodule. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunThe EIC-debounce sub-module provides up to 8 source input signal 11*4882a593Smuzhiyunconnections. A debounce mechanism is used to capture the input signals' 12*4882a593Smuzhiyunstable status (millisecond resolution) and a single-trigger mechanism 13*4882a593Smuzhiyunis introduced into this sub-module to enhance the input event detection 14*4882a593Smuzhiyunreliability. In addition, this sub-module's clock can be shut off 15*4882a593Smuzhiyunautomatically to reduce power dissipation. Moreover the debounce range 16*4882a593Smuzhiyunis from 1ms to 4s with a step size of 1ms. The input signal will be 17*4882a593Smuzhiyunignored if it is asserted for less than 1 ms. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunThe EIC-latch sub-module is used to latch some special power down signals 20*4882a593Smuzhiyunand generate interrupts, since the EIC-latch does not depend on the APB 21*4882a593Smuzhiyunclock to capture signals. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunThe EIC-async sub-module uses a 32kHz clock to capture the short signals 24*4882a593Smuzhiyun(microsecond resolution) to generate interrupts by level or edge trigger. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunThe EIC-sync is similar with GPIO's input function, which is a synchronized 27*4882a593Smuzhiyunsignal input register. It can generate interrupts by level or edge trigger 28*4882a593Smuzhiyunwhen detecting input signals. 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunRequired properties: 31*4882a593Smuzhiyun- compatible: Should be one of the following: 32*4882a593Smuzhiyun "sprd,sc9860-eic-debounce", 33*4882a593Smuzhiyun "sprd,sc9860-eic-latch", 34*4882a593Smuzhiyun "sprd,sc9860-eic-async", 35*4882a593Smuzhiyun "sprd,sc9860-eic-sync", 36*4882a593Smuzhiyun "sprd,sc2731-eic". 37*4882a593Smuzhiyun- reg: Define the base and range of the I/O address space containing 38*4882a593Smuzhiyun the GPIO controller registers. 39*4882a593Smuzhiyun- gpio-controller: Marks the device node as a GPIO controller. 40*4882a593Smuzhiyun- #gpio-cells: Should be <2>. The first cell is the gpio number and 41*4882a593Smuzhiyun the second cell is used to specify optional parameters. 42*4882a593Smuzhiyun- interrupt-controller: Marks the device node as an interrupt controller. 43*4882a593Smuzhiyun- #interrupt-cells: Should be <2>. Specifies the number of cells needed 44*4882a593Smuzhiyun to encode interrupt source. 45*4882a593Smuzhiyun- interrupts: Should be the port interrupt shared by all the gpios. 46*4882a593Smuzhiyun 47*4882a593SmuzhiyunExample: 48*4882a593Smuzhiyun eic_debounce: gpio@40210000 { 49*4882a593Smuzhiyun compatible = "sprd,sc9860-eic-debounce"; 50*4882a593Smuzhiyun reg = <0 0x40210000 0 0x80>; 51*4882a593Smuzhiyun gpio-controller; 52*4882a593Smuzhiyun #gpio-cells = <2>; 53*4882a593Smuzhiyun interrupt-controller; 54*4882a593Smuzhiyun #interrupt-cells = <2>; 55*4882a593Smuzhiyun interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun eic_latch: gpio@40210080 { 59*4882a593Smuzhiyun compatible = "sprd,sc9860-eic-latch"; 60*4882a593Smuzhiyun reg = <0 0x40210080 0 0x20>; 61*4882a593Smuzhiyun gpio-controller; 62*4882a593Smuzhiyun #gpio-cells = <2>; 63*4882a593Smuzhiyun interrupt-controller; 64*4882a593Smuzhiyun #interrupt-cells = <2>; 65*4882a593Smuzhiyun interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun eic_async: gpio@402100a0 { 69*4882a593Smuzhiyun compatible = "sprd,sc9860-eic-async"; 70*4882a593Smuzhiyun reg = <0 0x402100a0 0 0x20>; 71*4882a593Smuzhiyun gpio-controller; 72*4882a593Smuzhiyun #gpio-cells = <2>; 73*4882a593Smuzhiyun interrupt-controller; 74*4882a593Smuzhiyun #interrupt-cells = <2>; 75*4882a593Smuzhiyun interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun eic_sync: gpio@402100c0 { 79*4882a593Smuzhiyun compatible = "sprd,sc9860-eic-sync"; 80*4882a593Smuzhiyun reg = <0 0x402100c0 0 0x20>; 81*4882a593Smuzhiyun gpio-controller; 82*4882a593Smuzhiyun #gpio-cells = <2>; 83*4882a593Smuzhiyun interrupt-controller; 84*4882a593Smuzhiyun #interrupt-cells = <2>; 85*4882a593Smuzhiyun interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun pmic_eic: gpio@300 { 89*4882a593Smuzhiyun compatible = "sprd,sc2731-eic"; 90*4882a593Smuzhiyun reg = <0x300>; 91*4882a593Smuzhiyun interrupt-parent = <&sc2731_pmic>; 92*4882a593Smuzhiyun interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; 93*4882a593Smuzhiyun gpio-controller; 94*4882a593Smuzhiyun #gpio-cells = <2>; 95*4882a593Smuzhiyun interrupt-controller; 96*4882a593Smuzhiyun #interrupt-cells = <2>; 97*4882a593Smuzhiyun }; 98