1*4882a593SmuzhiyunDavinci/Keystone GPIO controller bindings 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired Properties: 4*4882a593Smuzhiyun- compatible: should be "ti,dm6441-gpio": for Davinci da850 SoCs 5*4882a593Smuzhiyun "ti,keystone-gpio": for Keystone 2 66AK2H/K, 66AK2L, 6*4882a593Smuzhiyun 66AK2E SoCs 7*4882a593Smuzhiyun "ti,k2g-gpio", "ti,keystone-gpio": for 66AK2G 8*4882a593Smuzhiyun "ti,am654-gpio", "ti,keystone-gpio": for TI K3 AM654 9*4882a593Smuzhiyun "ti,j721e-gpio", "ti,keystone-gpio": for J721E SoCs 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun- reg: Physical base address of the controller and the size of memory mapped 12*4882a593Smuzhiyun registers. 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun- gpio-controller : Marks the device node as a gpio controller. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- #gpio-cells : Should be two. 17*4882a593Smuzhiyun - first cell is the pin number 18*4882a593Smuzhiyun - second cell is used to specify optional parameters (unused) 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun- interrupts: Array of GPIO interrupt number. Only banked or unbanked IRQs are 21*4882a593Smuzhiyun supported at a time. 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun- ti,ngpio: The number of GPIO pins supported. 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun- ti,davinci-gpio-unbanked: The number of GPIOs that have an individual interrupt 26*4882a593Smuzhiyun line to processor. 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun- clocks: Should contain the device's input clock, and should be defined as per 29*4882a593Smuzhiyun the appropriate clock bindings consumer usage in, 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun Documentation/devicetree/bindings/clock/keystone-gate.txt 32*4882a593Smuzhiyun for 66AK2HK/66AK2L/66AK2E SoCs or, 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun Documentation/devicetree/bindings/clock/ti,sci-clk.txt 35*4882a593Smuzhiyun for 66AK2G SoCs 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun- clock-names: Name should be "gpio"; 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunCurrently clock-names and clocks are needed for all keystone 2 platforms 40*4882a593SmuzhiyunDavinci platforms do not have DT clocks as of now. 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunThe GPIO controller also acts as an interrupt controller. It uses the default 43*4882a593Smuzhiyuntwo cells specifier as described in Documentation/devicetree/bindings/ 44*4882a593Smuzhiyuninterrupt-controller/interrupts.txt. 45*4882a593Smuzhiyun 46*4882a593SmuzhiyunExample: 47*4882a593Smuzhiyun 48*4882a593Smuzhiyungpio: gpio@1e26000 { 49*4882a593Smuzhiyun compatible = "ti,dm6441-gpio"; 50*4882a593Smuzhiyun gpio-controller; 51*4882a593Smuzhiyun #gpio-cells = <2>; 52*4882a593Smuzhiyun reg = <0x226000 0x1000>; 53*4882a593Smuzhiyun interrupt-parent = <&intc>; 54*4882a593Smuzhiyun interrupts = <42 IRQ_TYPE_EDGE_BOTH 43 IRQ_TYPE_EDGE_BOTH 55*4882a593Smuzhiyun 44 IRQ_TYPE_EDGE_BOTH 45 IRQ_TYPE_EDGE_BOTH 56*4882a593Smuzhiyun 46 IRQ_TYPE_EDGE_BOTH 47 IRQ_TYPE_EDGE_BOTH 57*4882a593Smuzhiyun 48 IRQ_TYPE_EDGE_BOTH 49 IRQ_TYPE_EDGE_BOTH 58*4882a593Smuzhiyun 50 IRQ_TYPE_EDGE_BOTH>; 59*4882a593Smuzhiyun ti,ngpio = <144>; 60*4882a593Smuzhiyun ti,davinci-gpio-unbanked = <0>; 61*4882a593Smuzhiyun interrupt-controller; 62*4882a593Smuzhiyun #interrupt-cells = <2>; 63*4882a593Smuzhiyun}; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyunleds { 66*4882a593Smuzhiyun compatible = "gpio-leds"; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun led1 { 69*4882a593Smuzhiyun label = "davinci:green:usr1"; 70*4882a593Smuzhiyun gpios = <&gpio 10 GPIO_ACTIVE_HIGH>; 71*4882a593Smuzhiyun ... 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun led2 { 75*4882a593Smuzhiyun label = "davinci:red:debug1"; 76*4882a593Smuzhiyun gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; 77*4882a593Smuzhiyun ... 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun}; 80*4882a593Smuzhiyun 81*4882a593SmuzhiyunExample for 66AK2G: 82*4882a593Smuzhiyun 83*4882a593Smuzhiyungpio0: gpio@2603000 { 84*4882a593Smuzhiyun compatible = "ti,k2g-gpio", "ti,keystone-gpio"; 85*4882a593Smuzhiyun reg = <0x02603000 0x100>; 86*4882a593Smuzhiyun gpio-controller; 87*4882a593Smuzhiyun #gpio-cells = <2>; 88*4882a593Smuzhiyun interrupts = <GIC_SPI 432 IRQ_TYPE_EDGE_RISING>, 89*4882a593Smuzhiyun <GIC_SPI 433 IRQ_TYPE_EDGE_RISING>, 90*4882a593Smuzhiyun <GIC_SPI 434 IRQ_TYPE_EDGE_RISING>, 91*4882a593Smuzhiyun <GIC_SPI 435 IRQ_TYPE_EDGE_RISING>, 92*4882a593Smuzhiyun <GIC_SPI 436 IRQ_TYPE_EDGE_RISING>, 93*4882a593Smuzhiyun <GIC_SPI 437 IRQ_TYPE_EDGE_RISING>, 94*4882a593Smuzhiyun <GIC_SPI 438 IRQ_TYPE_EDGE_RISING>, 95*4882a593Smuzhiyun <GIC_SPI 439 IRQ_TYPE_EDGE_RISING>, 96*4882a593Smuzhiyun <GIC_SPI 440 IRQ_TYPE_EDGE_RISING>; 97*4882a593Smuzhiyun interrupt-controller; 98*4882a593Smuzhiyun #interrupt-cells = <2>; 99*4882a593Smuzhiyun ti,ngpio = <144>; 100*4882a593Smuzhiyun ti,davinci-gpio-unbanked = <0>; 101*4882a593Smuzhiyun clocks = <&k2g_clks 0x001b 0x0>; 102*4882a593Smuzhiyun clock-names = "gpio"; 103*4882a593Smuzhiyun}; 104*4882a593Smuzhiyun 105*4882a593SmuzhiyunExample for 66AK2HK/66AK2L/66AK2E: 106*4882a593Smuzhiyun 107*4882a593Smuzhiyungpio0: gpio@260bf00 { 108*4882a593Smuzhiyun compatible = "ti,keystone-gpio"; 109*4882a593Smuzhiyun reg = <0x0260bf00 0x100>; 110*4882a593Smuzhiyun gpio-controller; 111*4882a593Smuzhiyun #gpio-cells = <2>; 112*4882a593Smuzhiyun /* HW Interrupts mapped to GPIO pins */ 113*4882a593Smuzhiyun interrupts = <GIC_SPI 120 IRQ_TYPE_EDGE_RISING>, 114*4882a593Smuzhiyun <GIC_SPI 121 IRQ_TYPE_EDGE_RISING>, 115*4882a593Smuzhiyun <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 116*4882a593Smuzhiyun <GIC_SPI 123 IRQ_TYPE_EDGE_RISING>, 117*4882a593Smuzhiyun <GIC_SPI 124 IRQ_TYPE_EDGE_RISING>, 118*4882a593Smuzhiyun <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 119*4882a593Smuzhiyun <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 120*4882a593Smuzhiyun <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 121*4882a593Smuzhiyun <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 122*4882a593Smuzhiyun <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 123*4882a593Smuzhiyun <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 124*4882a593Smuzhiyun <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 125*4882a593Smuzhiyun <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 126*4882a593Smuzhiyun <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 127*4882a593Smuzhiyun <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 128*4882a593Smuzhiyun <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 129*4882a593Smuzhiyun <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 130*4882a593Smuzhiyun <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 131*4882a593Smuzhiyun <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 132*4882a593Smuzhiyun <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 133*4882a593Smuzhiyun <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>, 134*4882a593Smuzhiyun <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 135*4882a593Smuzhiyun <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>, 136*4882a593Smuzhiyun <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>, 137*4882a593Smuzhiyun <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>, 138*4882a593Smuzhiyun <GIC_SPI 145 IRQ_TYPE_EDGE_RISING>, 139*4882a593Smuzhiyun <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>, 140*4882a593Smuzhiyun <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>, 141*4882a593Smuzhiyun <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>, 142*4882a593Smuzhiyun <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 143*4882a593Smuzhiyun <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>, 144*4882a593Smuzhiyun <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 145*4882a593Smuzhiyun clocks = <&clkgpio>; 146*4882a593Smuzhiyun clock-names = "gpio"; 147*4882a593Smuzhiyun ti,ngpio = <32>; 148*4882a593Smuzhiyun ti,davinci-gpio-unbanked = <32>; 149*4882a593Smuzhiyun}; 150*4882a593Smuzhiyun 151*4882a593SmuzhiyunExample for K3 AM654: 152*4882a593Smuzhiyun 153*4882a593Smuzhiyunwkup_gpio0: wkup_gpio0@42110000 { 154*4882a593Smuzhiyun compatible = "ti,am654-gpio", "ti,keystone-gpio"; 155*4882a593Smuzhiyun reg = <0x42110000 0x100>; 156*4882a593Smuzhiyun gpio-controller; 157*4882a593Smuzhiyun #gpio-cells = <2>; 158*4882a593Smuzhiyun interrupt-parent = <&intr_wkup_gpio>; 159*4882a593Smuzhiyun interrupts = <59 128>, <59 129>, <59 130>, <59 131>; 160*4882a593Smuzhiyun interrupt-controller; 161*4882a593Smuzhiyun #interrupt-cells = <2>; 162*4882a593Smuzhiyun ti,ngpio = <56>; 163*4882a593Smuzhiyun ti,davinci-gpio-unbanked = <0>; 164*4882a593Smuzhiyun clocks = <&k3_clks 59 0>; 165*4882a593Smuzhiyun clock-names = "gpio"; 166*4882a593Smuzhiyun}; 167