1*4882a593SmuzhiyunAXP209 GPIO & pinctrl controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis driver follows the usual GPIO bindings found in 4*4882a593SmuzhiyunDocumentation/devicetree/bindings/gpio/gpio.txt 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThis driver follows the usual pinctrl bindings found in 7*4882a593SmuzhiyunDocumentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt 8*4882a593Smuzhiyun 9*4882a593SmuzhiyunThis driver employs the per-pin muxing pattern. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties: 12*4882a593Smuzhiyun- compatible: Should be one of: 13*4882a593Smuzhiyun - "x-powers,axp209-gpio" 14*4882a593Smuzhiyun - "x-powers,axp813-gpio" 15*4882a593Smuzhiyun- #gpio-cells: Should be two. The first cell is the pin number and the 16*4882a593Smuzhiyun second is the GPIO flags. 17*4882a593Smuzhiyun- gpio-controller: Marks the device node as a GPIO controller. 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunThis node must be a subnode of the axp20x PMIC, documented in 20*4882a593SmuzhiyunDocumentation/devicetree/bindings/mfd/axp20x.txt 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExample: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunaxp209: pmic@34 { 25*4882a593Smuzhiyun compatible = "x-powers,axp209"; 26*4882a593Smuzhiyun reg = <0x34>; 27*4882a593Smuzhiyun interrupt-parent = <&nmi_intc>; 28*4882a593Smuzhiyun interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 29*4882a593Smuzhiyun interrupt-controller; 30*4882a593Smuzhiyun #interrupt-cells = <1>; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun axp_gpio: gpio { 33*4882a593Smuzhiyun compatible = "x-powers,axp209-gpio"; 34*4882a593Smuzhiyun gpio-controller; 35*4882a593Smuzhiyun #gpio-cells = <2>; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun}; 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunThe GPIOs can be muxed to other functions and therefore, must be a subnode of 40*4882a593Smuzhiyunaxp_gpio. 41*4882a593Smuzhiyun 42*4882a593SmuzhiyunExample: 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun&axp_gpio { 45*4882a593Smuzhiyun gpio0_adc: gpio0-adc { 46*4882a593Smuzhiyun pins = "GPIO0"; 47*4882a593Smuzhiyun function = "adc"; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun}; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun&example_node { 52*4882a593Smuzhiyun pinctrl-names = "default"; 53*4882a593Smuzhiyun pinctrl-0 = <&gpio0_adc>; 54*4882a593Smuzhiyun}; 55*4882a593Smuzhiyun 56*4882a593SmuzhiyunGPIOs and their functions 57*4882a593Smuzhiyun------------------------- 58*4882a593Smuzhiyun 59*4882a593SmuzhiyunEach GPIO is independent from the other (i.e. GPIO0 in gpio_in function does 60*4882a593Smuzhiyunnot force GPIO1 and GPIO2 to be in gpio_in function as well). 61*4882a593Smuzhiyun 62*4882a593Smuzhiyunaxp209 63*4882a593Smuzhiyun------ 64*4882a593SmuzhiyunGPIO | Functions 65*4882a593Smuzhiyun------------------------ 66*4882a593SmuzhiyunGPIO0 | gpio_in, gpio_out, ldo, adc 67*4882a593SmuzhiyunGPIO1 | gpio_in, gpio_out, ldo, adc 68*4882a593SmuzhiyunGPIO2 | gpio_in, gpio_out 69*4882a593Smuzhiyun 70*4882a593Smuzhiyunaxp813 71*4882a593Smuzhiyun------ 72*4882a593SmuzhiyunGPIO | Functions 73*4882a593Smuzhiyun------------------------ 74*4882a593SmuzhiyunGPIO0 | gpio_in, gpio_out, ldo, adc 75*4882a593SmuzhiyunGPIO1 | gpio_in, gpio_out, ldo 76