1*4882a593SmuzhiyunBinding for Qualcomm Atheros AR7xxx/AR9xxx GPIO controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: has to be "qca,<soctype>-gpio" and one of the following 5*4882a593Smuzhiyun fallbacks: 6*4882a593Smuzhiyun - "qca,ar7100-gpio" 7*4882a593Smuzhiyun - "qca,ar9340-gpio" 8*4882a593Smuzhiyun- reg: Base address and size of the controllers memory area 9*4882a593Smuzhiyun- gpio-controller : Marks the device node as a GPIO controller. 10*4882a593Smuzhiyun- #gpio-cells : Should be two. The first cell is the pin number and the 11*4882a593Smuzhiyun second cell is used to specify optional parameters. 12*4882a593Smuzhiyun- ngpios: Should be set to the number of GPIOs available on the SoC. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunOptional properties: 15*4882a593Smuzhiyun- interrupts: Interrupt specifier for the controllers interrupt. 16*4882a593Smuzhiyun- interrupt-controller : Identifies the node as an interrupt controller 17*4882a593Smuzhiyun- #interrupt-cells : Specifies the number of cells needed to encode interrupt 18*4882a593Smuzhiyun source, should be 2 19*4882a593Smuzhiyun 20*4882a593SmuzhiyunPlease refer to interrupts.txt in this directory for details of the common 21*4882a593SmuzhiyunInterrupt Controllers bindings used by client devices. 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun gpio@18040000 { 26*4882a593Smuzhiyun compatible = "qca,ar9132-gpio", "qca,ar7100-gpio"; 27*4882a593Smuzhiyun reg = <0x18040000 0x30>; 28*4882a593Smuzhiyun interrupts = <2>; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun ngpios = <22>; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun gpio-controller; 33*4882a593Smuzhiyun #gpio-cells = <2>; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun interrupt-controller; 36*4882a593Smuzhiyun #interrupt-cells = <2>; 37*4882a593Smuzhiyun }; 38