1*4882a593Smuzhiyun* 74XX MMIO GPIO driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should contain one of the following: 5*4882a593Smuzhiyun "ti,741g125": for 741G125 (1-bit Input), 6*4882a593Smuzhiyun "ti,741g174": for 741G74 (1-bit Output), 7*4882a593Smuzhiyun "ti,742g125": for 742G125 (2-bit Input), 8*4882a593Smuzhiyun "ti,7474" : for 7474 (2-bit Output), 9*4882a593Smuzhiyun "ti,74125" : for 74125 (4-bit Input), 10*4882a593Smuzhiyun "ti,74175" : for 74175 (4-bit Output), 11*4882a593Smuzhiyun "ti,74365" : for 74365 (6-bit Input), 12*4882a593Smuzhiyun "ti,74174" : for 74174 (6-bit Output), 13*4882a593Smuzhiyun "ti,74244" : for 74244 (8-bit Input), 14*4882a593Smuzhiyun "ti,74273" : for 74273 (8-bit Output), 15*4882a593Smuzhiyun "ti,741624" : for 741624 (16-bit Input), 16*4882a593Smuzhiyun "ti,7416374": for 7416374 (16-bit Output). 17*4882a593Smuzhiyun- reg: Physical base address and length where IC resides. 18*4882a593Smuzhiyun- gpio-controller: Marks the device node as a gpio controller. 19*4882a593Smuzhiyun- #gpio-cells: Should be two. The first cell is the pin number and 20*4882a593Smuzhiyun the second cell is used to specify the GPIO polarity: 21*4882a593Smuzhiyun 0 = Active High, 22*4882a593Smuzhiyun 1 = Active Low. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyun ctrl: gpio@30008004 { 26*4882a593Smuzhiyun compatible = "ti,74174"; 27*4882a593Smuzhiyun reg = <0x30008004 0x1>; 28*4882a593Smuzhiyun gpio-controller; 29*4882a593Smuzhiyun #gpio-cells = <2>; 30*4882a593Smuzhiyun }; 31