1*4882a593Smuzhiyun* Generic 8-bits shift register GPIO driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible: Should contain one of the following: 5*4882a593Smuzhiyun "fairchild,74hc595" 6*4882a593Smuzhiyun "nxp,74lvc594" 7*4882a593Smuzhiyun- reg : chip select number 8*4882a593Smuzhiyun- gpio-controller : Marks the device node as a gpio controller. 9*4882a593Smuzhiyun- #gpio-cells : Should be two. The first cell is the pin number and 10*4882a593Smuzhiyun the second cell is used to specify the gpio polarity: 11*4882a593Smuzhiyun 0 = active high 12*4882a593Smuzhiyun 1 = active low 13*4882a593Smuzhiyun- registers-number: Number of daisy-chained shift registers 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun- enable-gpios: GPIO connected to the OE (Output Enable) pin. 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunExample: 19*4882a593Smuzhiyun 20*4882a593Smuzhiyungpio5: gpio5@0 { 21*4882a593Smuzhiyun compatible = "fairchild,74hc595"; 22*4882a593Smuzhiyun reg = <0>; 23*4882a593Smuzhiyun gpio-controller; 24*4882a593Smuzhiyun #gpio-cells = <2>; 25*4882a593Smuzhiyun registers-number = <4>; 26*4882a593Smuzhiyun spi-max-frequency = <100000>; 27*4882a593Smuzhiyun}; 28