1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/gpio/fsl-imx-gpio.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: Freescale i.MX/MXC GPIO controller 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Anson Huang <Anson.Huang@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyunproperties: 13*4882a593Smuzhiyun compatible: 14*4882a593Smuzhiyun oneOf: 15*4882a593Smuzhiyun - enum: 16*4882a593Smuzhiyun - fsl,imx1-gpio 17*4882a593Smuzhiyun - fsl,imx21-gpio 18*4882a593Smuzhiyun - fsl,imx31-gpio 19*4882a593Smuzhiyun - fsl,imx35-gpio 20*4882a593Smuzhiyun - fsl,imx7d-gpio 21*4882a593Smuzhiyun - items: 22*4882a593Smuzhiyun - const: fsl,imx35-gpio 23*4882a593Smuzhiyun - const: fsl,imx31-gpio 24*4882a593Smuzhiyun - items: 25*4882a593Smuzhiyun - enum: 26*4882a593Smuzhiyun - fsl,imx50-gpio 27*4882a593Smuzhiyun - fsl,imx51-gpio 28*4882a593Smuzhiyun - fsl,imx53-gpio 29*4882a593Smuzhiyun - fsl,imx6q-gpio 30*4882a593Smuzhiyun - fsl,imx6sl-gpio 31*4882a593Smuzhiyun - fsl,imx6sll-gpio 32*4882a593Smuzhiyun - fsl,imx6sx-gpio 33*4882a593Smuzhiyun - fsl,imx6ul-gpio 34*4882a593Smuzhiyun - fsl,imx7d-gpio 35*4882a593Smuzhiyun - fsl,imx8mm-gpio 36*4882a593Smuzhiyun - fsl,imx8mn-gpio 37*4882a593Smuzhiyun - fsl,imx8mp-gpio 38*4882a593Smuzhiyun - fsl,imx8mq-gpio 39*4882a593Smuzhiyun - fsl,imx8qxp-gpio 40*4882a593Smuzhiyun - const: fsl,imx35-gpio 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun reg: 43*4882a593Smuzhiyun maxItems: 1 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun interrupts: 46*4882a593Smuzhiyun description: | 47*4882a593Smuzhiyun Should be the port interrupt shared by all 32 pins, if one number. 48*4882a593Smuzhiyun If two numbers, the first one is the interrupt shared by low 16 pins 49*4882a593Smuzhiyun and the second one is for high 16 pins. 50*4882a593Smuzhiyun minItems: 1 51*4882a593Smuzhiyun maxItems: 2 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun interrupt-controller: true 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun "#interrupt-cells": 56*4882a593Smuzhiyun const: 2 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun clocks: 59*4882a593Smuzhiyun maxItems: 1 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun "#gpio-cells": 62*4882a593Smuzhiyun const: 2 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun gpio-controller: true 65*4882a593Smuzhiyun gpio-line-names: true 66*4882a593Smuzhiyun gpio-ranges: true 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun power-domains: 69*4882a593Smuzhiyun maxItems: 1 70*4882a593Smuzhiyun 71*4882a593SmuzhiyunpatternProperties: 72*4882a593Smuzhiyun "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$": 73*4882a593Smuzhiyun type: object 74*4882a593Smuzhiyun properties: 75*4882a593Smuzhiyun gpio-hog: true 76*4882a593Smuzhiyun gpios: true 77*4882a593Smuzhiyun input: true 78*4882a593Smuzhiyun output-high: true 79*4882a593Smuzhiyun output-low: true 80*4882a593Smuzhiyun line-name: true 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun required: 83*4882a593Smuzhiyun - gpio-hog 84*4882a593Smuzhiyun - gpios 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun additionalProperties: false 87*4882a593Smuzhiyun 88*4882a593Smuzhiyunrequired: 89*4882a593Smuzhiyun - compatible 90*4882a593Smuzhiyun - reg 91*4882a593Smuzhiyun - interrupts 92*4882a593Smuzhiyun - interrupt-controller 93*4882a593Smuzhiyun - "#interrupt-cells" 94*4882a593Smuzhiyun - "#gpio-cells" 95*4882a593Smuzhiyun - gpio-controller 96*4882a593Smuzhiyun 97*4882a593SmuzhiyunadditionalProperties: false 98*4882a593Smuzhiyun 99*4882a593Smuzhiyunexamples: 100*4882a593Smuzhiyun - | 101*4882a593Smuzhiyun gpio0: gpio@73f84000 { 102*4882a593Smuzhiyun compatible = "fsl,imx35-gpio"; 103*4882a593Smuzhiyun reg = <0x73f84000 0x4000>; 104*4882a593Smuzhiyun interrupts = <50 51>; 105*4882a593Smuzhiyun gpio-controller; 106*4882a593Smuzhiyun #gpio-cells = <2>; 107*4882a593Smuzhiyun interrupt-controller; 108*4882a593Smuzhiyun #interrupt-cells = <2>; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun... 112