1*4882a593SmuzhiyunBroadcom STB "UPG GIO" GPIO controller 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe controller's registers are organized as sets of eight 32-bit 4*4882a593Smuzhiyunregisters with each set controlling a bank of up to 32 pins. A single 5*4882a593Smuzhiyuninterrupt is shared for all of the banks handled by the controller. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun- compatible: 10*4882a593Smuzhiyun Must be "brcm,brcmstb-gpio" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun- reg: 13*4882a593Smuzhiyun Define the base and range of the I/O address space containing 14*4882a593Smuzhiyun the brcmstb GPIO controller registers 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun- #gpio-cells: 17*4882a593Smuzhiyun Should be <2>. The first cell is the pin number (within the controller's 18*4882a593Smuzhiyun pin space), and the second is used for the following: 19*4882a593Smuzhiyun bit[0]: polarity (0 for active-high, 1 for active-low) 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun- gpio-controller: 22*4882a593Smuzhiyun Specifies that the node is a GPIO controller. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun- brcm,gpio-bank-widths: 25*4882a593Smuzhiyun Number of GPIO lines for each bank. Number of elements must 26*4882a593Smuzhiyun correspond to number of banks suggested by the 'reg' property. 27*4882a593Smuzhiyun 28*4882a593SmuzhiyunOptional properties: 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun- interrupts: 31*4882a593Smuzhiyun The interrupt shared by all GPIO lines for this controller. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun- interrupts-extended: 34*4882a593Smuzhiyun Alternate form of specifying interrupts and parents that allows for 35*4882a593Smuzhiyun multiple parents. This takes precedence over 'interrupts' and 36*4882a593Smuzhiyun 'interrupt-parent'. Wakeup-capable GPIO controllers often route their 37*4882a593Smuzhiyun wakeup interrupt lines through a different interrupt controller than the 38*4882a593Smuzhiyun primary interrupt line, making this property necessary. 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun- #interrupt-cells: 41*4882a593Smuzhiyun Should be <2>. The first cell is the GPIO number, the second should specify 42*4882a593Smuzhiyun flags. The following subset of flags is supported: 43*4882a593Smuzhiyun - bits[3:0] trigger type and level flags 44*4882a593Smuzhiyun 1 = low-to-high edge triggered 45*4882a593Smuzhiyun 2 = high-to-low edge triggered 46*4882a593Smuzhiyun 4 = active high level-sensitive 47*4882a593Smuzhiyun 8 = active low level-sensitive 48*4882a593Smuzhiyun Valid combinations are 1, 2, 3, 4, 8. 49*4882a593Smuzhiyun See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun- interrupt-controller: 52*4882a593Smuzhiyun Marks the device node as an interrupt controller 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun- wakeup-source: 55*4882a593Smuzhiyun GPIOs for this controller can be used as a wakeup source 56*4882a593Smuzhiyun 57*4882a593SmuzhiyunExample: 58*4882a593Smuzhiyun upg_gio: gpio@f040a700 { 59*4882a593Smuzhiyun #gpio-cells = <2>; 60*4882a593Smuzhiyun #interrupt-cells = <2>; 61*4882a593Smuzhiyun compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 62*4882a593Smuzhiyun gpio-controller; 63*4882a593Smuzhiyun interrupt-controller; 64*4882a593Smuzhiyun reg = <0xf040a700 0x80>; 65*4882a593Smuzhiyun interrupt-parent = <&irq0_intc>; 66*4882a593Smuzhiyun interrupts = <0x6>; 67*4882a593Smuzhiyun brcm,gpio-bank-widths = <32 32 32 24>; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun upg_gio_aon: gpio@f04172c0 { 71*4882a593Smuzhiyun #gpio-cells = <2>; 72*4882a593Smuzhiyun #interrupt-cells = <2>; 73*4882a593Smuzhiyun compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio"; 74*4882a593Smuzhiyun gpio-controller; 75*4882a593Smuzhiyun interrupt-controller; 76*4882a593Smuzhiyun reg = <0xf04172c0 0x40>; 77*4882a593Smuzhiyun interrupt-parent = <&irq0_aon_intc>; 78*4882a593Smuzhiyun interrupts = <0x6>; 79*4882a593Smuzhiyun interrupts-extended = <&irq0_aon_intc 0x6>, 80*4882a593Smuzhiyun <&aon_pm_l2_intc 0x5>; 81*4882a593Smuzhiyun wakeup-source; 82*4882a593Smuzhiyun brcm,gpio-bank-widths = <18 4>; 83*4882a593Smuzhiyun }; 84