1*4882a593SmuzhiyunGPIO controllers on MPC8xxx SoCs 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThis is for the non-QE/CPM/GUTs GPIO controllers as found on 4*4882a593Smuzhiyun8349, 8572, 8610 and compatible. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunEvery GPIO controller node must have #gpio-cells property defined, 7*4882a593Smuzhiyunthis information will be used to translate gpio-specifiers. 8*4882a593SmuzhiyunSee bindings/gpio/gpio.txt for details of how to specify GPIO 9*4882a593Smuzhiyuninformation for devices. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunThe GPIO module usually is connected to the SoC's internal interrupt 12*4882a593Smuzhiyuncontroller, see bindings/interrupt-controller/interrupts.txt (the 13*4882a593Smuzhiyuninterrupt client nodes section) for details how to specify this GPIO 14*4882a593Smuzhiyunmodule's interrupt. 15*4882a593Smuzhiyun 16*4882a593SmuzhiyunThe GPIO module may serve as another interrupt controller (cascaded to 17*4882a593Smuzhiyunthe SoC's internal interrupt controller). See the interrupt controller 18*4882a593Smuzhiyunnodes section in bindings/interrupt-controller/interrupts.txt for 19*4882a593Smuzhiyundetails. 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunRequired properties: 22*4882a593Smuzhiyun- compatible: "fsl,<chip>-gpio" followed by "fsl,mpc8349-gpio" 23*4882a593Smuzhiyun for 83xx, "fsl,mpc8572-gpio" for 85xx, or 24*4882a593Smuzhiyun "fsl,mpc8610-gpio" for 86xx. 25*4882a593Smuzhiyun- #gpio-cells: Should be two. The first cell is the pin number 26*4882a593Smuzhiyun and the second cell is used to specify optional 27*4882a593Smuzhiyun parameters (currently unused). 28*4882a593Smuzhiyun- interrupts: Interrupt mapping for GPIO IRQ. 29*4882a593Smuzhiyun- gpio-controller: Marks the port as GPIO controller. 30*4882a593Smuzhiyun 31*4882a593SmuzhiyunOptional properties: 32*4882a593Smuzhiyun- interrupt-controller: Empty boolean property which marks the GPIO 33*4882a593Smuzhiyun module as an IRQ controller. 34*4882a593Smuzhiyun- #interrupt-cells: Should be two. Defines the number of integer 35*4882a593Smuzhiyun cells required to specify an interrupt within 36*4882a593Smuzhiyun this interrupt controller. The first cell 37*4882a593Smuzhiyun defines the pin number, the second cell 38*4882a593Smuzhiyun defines additional flags (trigger type, 39*4882a593Smuzhiyun trigger polarity). Note that the available 40*4882a593Smuzhiyun set of trigger conditions supported by the 41*4882a593Smuzhiyun GPIO module depends on the actual SoC. 42*4882a593Smuzhiyun 43*4882a593SmuzhiyunExample of gpio-controller nodes for a MPC8347 SoC: 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun gpio1: gpio-controller@c00 { 46*4882a593Smuzhiyun #gpio-cells = <2>; 47*4882a593Smuzhiyun compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; 48*4882a593Smuzhiyun reg = <0xc00 0x100>; 49*4882a593Smuzhiyun interrupt-parent = <&ipic>; 50*4882a593Smuzhiyun interrupts = <74 0x8>; 51*4882a593Smuzhiyun gpio-controller; 52*4882a593Smuzhiyun interrupt-controller; 53*4882a593Smuzhiyun #interrupt-cells = <2>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun gpio2: gpio-controller@d00 { 57*4882a593Smuzhiyun #gpio-cells = <2>; 58*4882a593Smuzhiyun compatible = "fsl,mpc8347-gpio", "fsl,mpc8349-gpio"; 59*4882a593Smuzhiyun reg = <0xd00 0x100>; 60*4882a593Smuzhiyun interrupt-parent = <&ipic>; 61*4882a593Smuzhiyun interrupts = <75 0x8>; 62*4882a593Smuzhiyun gpio-controller; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593SmuzhiyunExample of a peripheral using the GPIO module as an IRQ controller: 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun funkyfpga@0 { 68*4882a593Smuzhiyun compatible = "funky-fpga"; 69*4882a593Smuzhiyun ... 70*4882a593Smuzhiyun interrupt-parent = <&gpio1>; 71*4882a593Smuzhiyun interrupts = <4 3>; 72*4882a593Smuzhiyun }; 73