1*4882a593SmuzhiyunNVIDIA Tegra20/Tegra30/Tegr114/Tegra124 fuse block. 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- compatible : For Tegra20, must contain "nvidia,tegra20-efuse". For Tegra30, 5*4882a593Smuzhiyun must contain "nvidia,tegra30-efuse". For Tegra114, must contain 6*4882a593Smuzhiyun "nvidia,tegra114-efuse". For Tegra124, must contain "nvidia,tegra124-efuse". 7*4882a593Smuzhiyun For Tegra132 must contain "nvidia,tegra132-efuse", "nvidia,tegra124-efuse". 8*4882a593Smuzhiyun For Tegra210 must contain "nvidia,tegra210-efuse". For Tegra186 must contain 9*4882a593Smuzhiyun "nvidia,tegra186-efuse". For Tegra194 must contain "nvidia,tegra194-efuse". 10*4882a593Smuzhiyun For Tegra234 must contain "nvidia,tegra234-efuse". 11*4882a593Smuzhiyun Details: 12*4882a593Smuzhiyun nvidia,tegra20-efuse: Tegra20 requires using APB DMA to read the fuse data 13*4882a593Smuzhiyun due to a hardware bug. Tegra20 also lacks certain information which is 14*4882a593Smuzhiyun available in later generations such as fab code, lot code, wafer id,.. 15*4882a593Smuzhiyun nvidia,tegra30-efuse, nvidia,tegra114-efuse and nvidia,tegra124-efuse: 16*4882a593Smuzhiyun The differences between these SoCs are the size of the efuse array, 17*4882a593Smuzhiyun the location of the spare (OEM programmable) bits and the location of 18*4882a593Smuzhiyun the speedo data. 19*4882a593Smuzhiyun- reg: Should contain 1 entry: the entry gives the physical address and length 20*4882a593Smuzhiyun of the fuse registers. 21*4882a593Smuzhiyun- clocks: Must contain an entry for each entry in clock-names. 22*4882a593Smuzhiyun See ../clocks/clock-bindings.txt for details. 23*4882a593Smuzhiyun- clock-names: Must include the following entries: 24*4882a593Smuzhiyun - fuse 25*4882a593Smuzhiyun- resets: Must contain an entry for each entry in reset-names. 26*4882a593Smuzhiyun See ../reset/reset.txt for details. 27*4882a593Smuzhiyun- reset-names: Must include the following entries: 28*4882a593Smuzhiyun - fuse 29*4882a593Smuzhiyun 30*4882a593SmuzhiyunExample: 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun fuse@7000f800 { 33*4882a593Smuzhiyun compatible = "nvidia,tegra20-efuse"; 34*4882a593Smuzhiyun reg = <0x7000f800 0x400>, 35*4882a593Smuzhiyun <0x70000000 0x400>; 36*4882a593Smuzhiyun clocks = <&tegra_car TEGRA20_CLK_FUSE>; 37*4882a593Smuzhiyun clock-names = "fuse"; 38*4882a593Smuzhiyun resets = <&tegra_car 39>; 39*4882a593Smuzhiyun reset-names = "fuse"; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun 43