1*4882a593SmuzhiyunDevice-tree bindings for AST2600 FSI master 2*4882a593Smuzhiyun------------------------------------------- 3*4882a593Smuzhiyun 4*4882a593SmuzhiyunThe AST2600 contains two identical FSI masters. They share a clock and have a 5*4882a593Smuzhiyunseparate interrupt line and output pins. 6*4882a593Smuzhiyun 7*4882a593SmuzhiyunRequired properties: 8*4882a593Smuzhiyun - compatible: "aspeed,ast2600-fsi-master" 9*4882a593Smuzhiyun - reg: base address and length 10*4882a593Smuzhiyun - clocks: phandle and clock number 11*4882a593Smuzhiyun - interrupts: platform dependent interrupt description 12*4882a593Smuzhiyun - pinctrl-0: phandle to pinctrl node 13*4882a593Smuzhiyun - pinctrl-names: pinctrl state 14*4882a593Smuzhiyun 15*4882a593SmuzhiyunOptional properties: 16*4882a593Smuzhiyun - cfam-reset-gpios: GPIO for CFAM reset 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun - fsi-routing-gpios: GPIO for setting the FSI mux (internal or cabled) 19*4882a593Smuzhiyun - fsi-mux-gpios: GPIO for detecting the desired FSI mux state 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunExamples: 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun fsi-master { 25*4882a593Smuzhiyun compatible = "aspeed,ast2600-fsi-master", "fsi-master"; 26*4882a593Smuzhiyun reg = <0x1e79b000 0x94>; 27*4882a593Smuzhiyun interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 28*4882a593Smuzhiyun pinctrl-names = "default"; 29*4882a593Smuzhiyun pinctrl-0 = <&pinctrl_fsi1_default>; 30*4882a593Smuzhiyun clocks = <&syscon ASPEED_CLK_GATE_FSICLK>; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun fsi-routing-gpios = <&gpio0 ASPEED_GPIO(Q, 7) GPIO_ACTIVE_HIGH>; 33*4882a593Smuzhiyun fsi-mux-gpios = <&gpio0 ASPEED_GPIO(B, 0) GPIO_ACTIVE_HIGH>; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_LOW>; 36*4882a593Smuzhiyun }; 37