1*4882a593SmuzhiyunXilinx Slave Serial SPI FPGA Manager 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunXilinx Spartan-6 and 7 Series FPGAs support a method of loading the 4*4882a593Smuzhiyunbitstream over what is referred to as "slave serial" interface. 5*4882a593SmuzhiyunThe slave serial link is not technically SPI, and might require extra 6*4882a593Smuzhiyuncircuits in order to play nicely with other SPI slaves on the same bus. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunSee: 9*4882a593Smuzhiyun- https://www.xilinx.com/support/documentation/user_guides/ug380.pdf 10*4882a593Smuzhiyun- https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf 11*4882a593Smuzhiyun- https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunRequired properties: 14*4882a593Smuzhiyun- compatible: should contain "xlnx,fpga-slave-serial" 15*4882a593Smuzhiyun- reg: spi chip select of the FPGA 16*4882a593Smuzhiyun- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual) 17*4882a593Smuzhiyun- done-gpios: config status pin (referred to as DONE in the manual) 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunOptional properties: 20*4882a593Smuzhiyun- init-b-gpios: initialization status and configuration error pin 21*4882a593Smuzhiyun (referred to as INIT_B in the manual) 22*4882a593Smuzhiyun 23*4882a593SmuzhiyunExample for full FPGA configuration: 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun fpga-region0 { 26*4882a593Smuzhiyun compatible = "fpga-region"; 27*4882a593Smuzhiyun fpga-mgr = <&fpga_mgr_spi>; 28*4882a593Smuzhiyun #address-cells = <0x1>; 29*4882a593Smuzhiyun #size-cells = <0x1>; 30*4882a593Smuzhiyun }; 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun spi1: spi@10680 { 33*4882a593Smuzhiyun compatible = "marvell,armada-xp-spi", "marvell,orion-spi"; 34*4882a593Smuzhiyun pinctrl-0 = <&spi0_pins>; 35*4882a593Smuzhiyun pinctrl-names = "default"; 36*4882a593Smuzhiyun #address-cells = <1>; 37*4882a593Smuzhiyun #size-cells = <0>; 38*4882a593Smuzhiyun cell-index = <1>; 39*4882a593Smuzhiyun interrupts = <92>; 40*4882a593Smuzhiyun clocks = <&coreclk 0>; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun fpga_mgr_spi: fpga-mgr@0 { 43*4882a593Smuzhiyun compatible = "xlnx,fpga-slave-serial"; 44*4882a593Smuzhiyun spi-max-frequency = <60000000>; 45*4882a593Smuzhiyun spi-cpha; 46*4882a593Smuzhiyun reg = <0>; 47*4882a593Smuzhiyun prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; 48*4882a593Smuzhiyun init-b-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; 49*4882a593Smuzhiyun done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun }; 52