1*4882a593SmuzhiyunXilinx LogiCORE Partial Reconfig Decoupler Softcore 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Xilinx LogiCORE Partial Reconfig Decoupler manages one or more 4*4882a593Smuzhiyundecouplers / fpga bridges. 5*4882a593SmuzhiyunThe controller can decouple/disable the bridges which prevents signal 6*4882a593Smuzhiyunchanges from passing through the bridge. The controller can also 7*4882a593Smuzhiyuncouple / enable the bridges which allows traffic to pass through the 8*4882a593Smuzhiyunbridge normally. 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunThe Driver supports only MMIO handling. A PR region can have multiple 11*4882a593SmuzhiyunPR Decouplers which can be handled independently or chained via decouple/ 12*4882a593Smuzhiyundecouple_status signals. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunRequired properties: 15*4882a593Smuzhiyun- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by 16*4882a593Smuzhiyun "xlnx,pr-decoupler" 17*4882a593Smuzhiyun- regs : base address and size for decoupler module 18*4882a593Smuzhiyun- clocks : input clock to IP 19*4882a593Smuzhiyun- clock-names : should contain "aclk" 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunSee Documentation/devicetree/bindings/fpga/fpga-region.txt and 22*4882a593SmuzhiyunDocumentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings. 23*4882a593Smuzhiyun 24*4882a593SmuzhiyunExample: 25*4882a593Smuzhiyun fpga-bridge@100000450 { 26*4882a593Smuzhiyun compatible = "xlnx,pr-decoupler-1.00", 27*4882a593Smuzhiyun "xlnx-pr-decoupler"; 28*4882a593Smuzhiyun regs = <0x10000045 0x10>; 29*4882a593Smuzhiyun clocks = <&clkc 15>; 30*4882a593Smuzhiyun clock-names = "aclk"; 31*4882a593Smuzhiyun bridge-enable = <0>; 32*4882a593Smuzhiyun }; 33