1*4882a593SmuzhiyunLattice MachXO2 Slave SPI FPGA Manager 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunLattice MachXO2 FPGAs support a method of loading the bitstream over 4*4882a593Smuzhiyun'slave SPI' interface. 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunSee 'MachXO2ProgrammingandConfigurationUsageGuide.pdf' on www.latticesemi.com 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunRequired properties: 9*4882a593Smuzhiyun- compatible: should contain "lattice,machxo2-slave-spi" 10*4882a593Smuzhiyun- reg: spi chip select of the FPGA 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunExample for full FPGA configuration: 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun fpga-region0 { 15*4882a593Smuzhiyun compatible = "fpga-region"; 16*4882a593Smuzhiyun fpga-mgr = <&fpga_mgr_spi>; 17*4882a593Smuzhiyun #address-cells = <0x1>; 18*4882a593Smuzhiyun #size-cells = <0x1>; 19*4882a593Smuzhiyun }; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun spi1: spi@2000 { 22*4882a593Smuzhiyun ... 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun fpga_mgr_spi: fpga-mgr@0 { 25*4882a593Smuzhiyun compatible = "lattice,machxo2-slave-spi"; 26*4882a593Smuzhiyun spi-max-frequency = <8000000>; 27*4882a593Smuzhiyun reg = <0>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun }; 30