xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593SmuzhiyunLattice iCE40 FPGA Manager
2*4882a593Smuzhiyun
3*4882a593SmuzhiyunRequired properties:
4*4882a593Smuzhiyun- compatible:		Should contain "lattice,ice40-fpga-mgr"
5*4882a593Smuzhiyun- reg:			SPI chip select
6*4882a593Smuzhiyun- spi-max-frequency:	Maximum SPI frequency (>=1000000, <=25000000)
7*4882a593Smuzhiyun- cdone-gpios:		GPIO input connected to CDONE pin
8*4882a593Smuzhiyun- reset-gpios:		Active-low GPIO output connected to CRESET_B pin. Note
9*4882a593Smuzhiyun			that unless the GPIO is held low during startup, the
10*4882a593Smuzhiyun			FPGA will enter Master SPI mode and drive SCK with a
11*4882a593Smuzhiyun			clock signal potentially jamming other devices on the
12*4882a593Smuzhiyun			bus until the firmware is loaded.
13*4882a593Smuzhiyun
14*4882a593SmuzhiyunExample:
15*4882a593Smuzhiyun	fpga: fpga@0 {
16*4882a593Smuzhiyun		compatible = "lattice,ice40-fpga-mgr";
17*4882a593Smuzhiyun		reg = <0>;
18*4882a593Smuzhiyun		spi-max-frequency = <1000000>;
19*4882a593Smuzhiyun		cdone-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
20*4882a593Smuzhiyun		reset-gpios = <&gpio 22 GPIO_ACTIVE_LOW>;
21*4882a593Smuzhiyun	};
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