1*4882a593SmuzhiyunAltera Passive Serial SPI FPGA Manager 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunAltera FPGAs support a method of loading the bitstream over what is 4*4882a593Smuzhiyunreferred to as "passive serial". 5*4882a593SmuzhiyunThe passive serial link is not technically SPI, and might require extra 6*4882a593Smuzhiyuncircuits in order to play nicely with other SPI slaves on the same bus. 7*4882a593Smuzhiyun 8*4882a593SmuzhiyunSee https://www.altera.com/literature/hb/cyc/cyc_c51013.pdf 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunRequired properties: 11*4882a593Smuzhiyun- compatible: Must be one of the following: 12*4882a593Smuzhiyun "altr,fpga-passive-serial", 13*4882a593Smuzhiyun "altr,fpga-arria10-passive-serial" 14*4882a593Smuzhiyun- reg: SPI chip select of the FPGA 15*4882a593Smuzhiyun- nconfig-gpios: config pin (referred to as nCONFIG in the manual) 16*4882a593Smuzhiyun- nstat-gpios: status pin (referred to as nSTATUS in the manual) 17*4882a593Smuzhiyun 18*4882a593SmuzhiyunOptional properties: 19*4882a593Smuzhiyun- confd-gpios: confd pin (referred to as CONF_DONE in the manual) 20*4882a593Smuzhiyun 21*4882a593SmuzhiyunExample: 22*4882a593Smuzhiyun fpga: fpga@0 { 23*4882a593Smuzhiyun compatible = "altr,fpga-passive-serial"; 24*4882a593Smuzhiyun spi-max-frequency = <20000000>; 25*4882a593Smuzhiyun reg = <0>; 26*4882a593Smuzhiyun nconfig-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>; 27*4882a593Smuzhiyun nstat-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>; 28*4882a593Smuzhiyun confd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; 29*4882a593Smuzhiyun }; 30