1*4882a593SmuzhiyunAltera FPGA/HPS Bridge Driver 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunRequired properties: 4*4882a593Smuzhiyun- regs : base address and size for AXI bridge module 5*4882a593Smuzhiyun- compatible : Should contain one of: 6*4882a593Smuzhiyun "altr,socfpga-lwhps2fpga-bridge", 7*4882a593Smuzhiyun "altr,socfpga-hps2fpga-bridge", or 8*4882a593Smuzhiyun "altr,socfpga-fpga2hps-bridge" 9*4882a593Smuzhiyun- resets : Phandle and reset specifier for this bridge's reset 10*4882a593Smuzhiyun- clocks : Clocks used by this module. 11*4882a593Smuzhiyun 12*4882a593SmuzhiyunSee Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings. 13*4882a593Smuzhiyun 14*4882a593SmuzhiyunExample: 15*4882a593Smuzhiyun fpga_bridge0: fpga-bridge@ff400000 { 16*4882a593Smuzhiyun compatible = "altr,socfpga-lwhps2fpga-bridge"; 17*4882a593Smuzhiyun reg = <0xff400000 0x100000>; 18*4882a593Smuzhiyun resets = <&rst LWHPS2FPGA_RESET>; 19*4882a593Smuzhiyun clocks = <&l4_main_clk>; 20*4882a593Smuzhiyun bridge-enable = <0>; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun fpga_bridge1: fpga-bridge@ff500000 { 24*4882a593Smuzhiyun compatible = "altr,socfpga-hps2fpga-bridge"; 25*4882a593Smuzhiyun reg = <0xff500000 0x10000>; 26*4882a593Smuzhiyun resets = <&rst HPS2FPGA_RESET>; 27*4882a593Smuzhiyun clocks = <&l4_main_clk>; 28*4882a593Smuzhiyun bridge-enable = <1>; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun fpga_bridge2: fpga-bridge@ff600000 { 32*4882a593Smuzhiyun compatible = "altr,socfpga-fpga2hps-bridge"; 33*4882a593Smuzhiyun reg = <0xff600000 0x100000>; 34*4882a593Smuzhiyun resets = <&rst FPGA2HPS_RESET>; 35*4882a593Smuzhiyun clocks = <&l4_main_clk>; 36*4882a593Smuzhiyun }; 37