1*4882a593SmuzhiyunNVIDIA Tegra210 Boot and Power Management Processor (BPMP) 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Boot and Power Management Processor (BPMP) is a co-processor found 4*4882a593Smuzhiyunin Tegra210 SoC. It is designed to handle the early stages of the boot 5*4882a593Smuzhiyunprocess as well as to assisting in entering deep low power state 6*4882a593Smuzhiyun(suspend to ram), and also offloading DRAM memory clock scaling on 7*4882a593Smuzhiyunsome platforms. The binding document defines the resources that would 8*4882a593Smuzhiyunbe used by the BPMP T210 firmware driver, which can create the 9*4882a593Smuzhiyuninterprocessor communication (IPC) between the CPU and BPMP. 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunRequired properties: 12*4882a593Smuzhiyun- compatible 13*4882a593Smuzhiyun Array of strings 14*4882a593Smuzhiyun One of: 15*4882a593Smuzhiyun - "nvidia,tegra210-bpmp" 16*4882a593Smuzhiyun- reg: physical base address and length for HW synchornization primitives 17*4882a593Smuzhiyun 1) base address and length to Tegra 'atomics' hardware 18*4882a593Smuzhiyun 2) base address and length to Tegra 'semaphore' hardware 19*4882a593Smuzhiyun- interrupts: specifies the interrupt number for receiving messages ("rx") 20*4882a593Smuzhiyun and for triggering messages ("tx") 21*4882a593Smuzhiyun 22*4882a593SmuzhiyunOptional properties: 23*4882a593Smuzhiyun- #clock-cells : Should be 1 for platforms where DRAM clock control is 24*4882a593Smuzhiyun offloaded to bpmp. 25*4882a593Smuzhiyun 26*4882a593SmuzhiyunExample: 27*4882a593Smuzhiyun 28*4882a593Smuzhiyunbpmp@70016000 { 29*4882a593Smuzhiyun compatible = "nvidia,tegra210-bpmp"; 30*4882a593Smuzhiyun reg = <0x0 0x70016000 0x0 0x2000 31*4882a593Smuzhiyun 0x0 0x60001000 0x0 0x1000>; 32*4882a593Smuzhiyun interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>, 33*4882a593Smuzhiyun <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 34*4882a593Smuzhiyun interrupt-names = "tx", "rx"; 35*4882a593Smuzhiyun}; 36