1*4882a593SmuzhiyunAspeed AST2500 SoC EDAC node 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunThe Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error 4*4882a593Smuzhiyuncorrection check). 5*4882a593Smuzhiyun 6*4882a593SmuzhiyunThe memory controller supports SECDED (single bit error correction, double bit 7*4882a593Smuzhiyunerror detection) and single bit error auto scrubbing by reserving 8 bits for 8*4882a593Smuzhiyunevery 64 bit word (effectively reducing available memory to 8/9). 9*4882a593Smuzhiyun 10*4882a593SmuzhiyunNote, the bootloader must configure ECC mode in the memory controller. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunRequired properties: 14*4882a593Smuzhiyun- compatible: should be "aspeed,ast2500-sdram-edac" 15*4882a593Smuzhiyun- reg: sdram controller register set should be <0x1e6e0000 0x174> 16*4882a593Smuzhiyun- interrupts: should be AVIC interrupt #0 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun 19*4882a593SmuzhiyunExample: 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun edac: sdram@1e6e0000 { 22*4882a593Smuzhiyun compatible = "aspeed,ast2500-sdram-edac"; 23*4882a593Smuzhiyun reg = <0x1e6e0000 0x174>; 24*4882a593Smuzhiyun interrupts = <0>; 25*4882a593Smuzhiyun }; 26