1*4882a593Smuzhiyun* APM X-Gene SoC EDAC node 2*4882a593Smuzhiyun 3*4882a593SmuzhiyunEDAC node is defined to describe on-chip error detection and correction. 4*4882a593SmuzhiyunThe follow error types are supported: 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun memory controller - Memory controller 7*4882a593Smuzhiyun PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache 8*4882a593Smuzhiyun L3 - L3 cache controller 9*4882a593Smuzhiyun SoC - SoC IP's such as Ethernet, SATA, and etc 10*4882a593Smuzhiyun 11*4882a593SmuzhiyunThe following section describes the EDAC DT node binding. 12*4882a593Smuzhiyun 13*4882a593SmuzhiyunRequired properties: 14*4882a593Smuzhiyun- compatible : Shall be "apm,xgene-edac". 15*4882a593Smuzhiyun- regmap-csw : Regmap of the CPU switch fabric (CSW) resource. 16*4882a593Smuzhiyun- regmap-mcba : Regmap of the MCB-A (memory bridge) resource. 17*4882a593Smuzhiyun- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. 18*4882a593Smuzhiyun- regmap-efuse : Regmap of the PMD efuse resource. 19*4882a593Smuzhiyun- regmap-rb : Regmap of the register bus resource. This property 20*4882a593Smuzhiyun is optional only for compatibility. If the RB 21*4882a593Smuzhiyun error conditions are not cleared, it will 22*4882a593Smuzhiyun continuously generate interrupt. 23*4882a593Smuzhiyun- reg : First resource shall be the CPU bus (PCP) resource. 24*4882a593Smuzhiyun- interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error 25*4882a593Smuzhiyun IRQ(s). 26*4882a593Smuzhiyun 27*4882a593SmuzhiyunRequired properties for memory controller subnode: 28*4882a593Smuzhiyun- compatible : Shall be "apm,xgene-edac-mc". 29*4882a593Smuzhiyun- reg : First resource shall be the memory controller unit 30*4882a593Smuzhiyun (MCU) resource. 31*4882a593Smuzhiyun- memory-controller : Instance number of the memory controller. 32*4882a593Smuzhiyun 33*4882a593SmuzhiyunRequired properties for PMD subnode: 34*4882a593Smuzhiyun- compatible : Shall be "apm,xgene-edac-pmd" or 35*4882a593Smuzhiyun "apm,xgene-edac-pmd-v2". 36*4882a593Smuzhiyun- reg : First resource shall be the PMD resource. 37*4882a593Smuzhiyun- pmd-controller : Instance number of the PMD controller. 38*4882a593Smuzhiyun 39*4882a593SmuzhiyunRequired properties for L3 subnode: 40*4882a593Smuzhiyun- compatible : Shall be "apm,xgene-edac-l3" or 41*4882a593Smuzhiyun "apm,xgene-edac-l3-v2". 42*4882a593Smuzhiyun- reg : First resource shall be the L3 EDAC resource. 43*4882a593Smuzhiyun 44*4882a593SmuzhiyunRequired properties for SoC subnode: 45*4882a593Smuzhiyun- compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or 46*4882a593Smuzhiyun "apm,xgene-edac-l3-soc" for general value reporting 47*4882a593Smuzhiyun only. 48*4882a593Smuzhiyun- reg : First resource shall be the SoC EDAC resource. 49*4882a593Smuzhiyun 50*4882a593SmuzhiyunExample: 51*4882a593Smuzhiyun csw: csw@7e200000 { 52*4882a593Smuzhiyun compatible = "apm,xgene-csw", "syscon"; 53*4882a593Smuzhiyun reg = <0x0 0x7e200000 0x0 0x1000>; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun mcba: mcba@7e700000 { 57*4882a593Smuzhiyun compatible = "apm,xgene-mcb", "syscon"; 58*4882a593Smuzhiyun reg = <0x0 0x7e700000 0x0 0x1000>; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun mcbb: mcbb@7e720000 { 62*4882a593Smuzhiyun compatible = "apm,xgene-mcb", "syscon"; 63*4882a593Smuzhiyun reg = <0x0 0x7e720000 0x0 0x1000>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun efuse: efuse@1054a000 { 67*4882a593Smuzhiyun compatible = "apm,xgene-efuse", "syscon"; 68*4882a593Smuzhiyun reg = <0x0 0x1054a000 0x0 0x20>; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun rb: rb@7e000000 { 72*4882a593Smuzhiyun compatible = "apm,xgene-rb", "syscon"; 73*4882a593Smuzhiyun reg = <0x0 0x7e000000 0x0 0x10>; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun edac@78800000 { 77*4882a593Smuzhiyun compatible = "apm,xgene-edac"; 78*4882a593Smuzhiyun #address-cells = <2>; 79*4882a593Smuzhiyun #size-cells = <2>; 80*4882a593Smuzhiyun ranges; 81*4882a593Smuzhiyun regmap-csw = <&csw>; 82*4882a593Smuzhiyun regmap-mcba = <&mcba>; 83*4882a593Smuzhiyun regmap-mcbb = <&mcbb>; 84*4882a593Smuzhiyun regmap-efuse = <&efuse>; 85*4882a593Smuzhiyun regmap-rb = <&rb>; 86*4882a593Smuzhiyun reg = <0x0 0x78800000 0x0 0x100>; 87*4882a593Smuzhiyun interrupts = <0x0 0x20 0x4>, 88*4882a593Smuzhiyun <0x0 0x21 0x4>, 89*4882a593Smuzhiyun <0x0 0x27 0x4>; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun edacmc@7e800000 { 92*4882a593Smuzhiyun compatible = "apm,xgene-edac-mc"; 93*4882a593Smuzhiyun reg = <0x0 0x7e800000 0x0 0x1000>; 94*4882a593Smuzhiyun memory-controller = <0>; 95*4882a593Smuzhiyun }; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun edacpmd@7c000000 { 98*4882a593Smuzhiyun compatible = "apm,xgene-edac-pmd"; 99*4882a593Smuzhiyun reg = <0x0 0x7c000000 0x0 0x200000>; 100*4882a593Smuzhiyun pmd-controller = <0>; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun edacl3@7e600000 { 104*4882a593Smuzhiyun compatible = "apm,xgene-edac-l3"; 105*4882a593Smuzhiyun reg = <0x0 0x7e600000 0x0 0x1000>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun edacsoc@7e930000 { 109*4882a593Smuzhiyun compatible = "apm,xgene-edac-soc-v1"; 110*4882a593Smuzhiyun reg = <0x0 0x7e930000 0x0 0x1000>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun }; 113