1*4882a593Smuzhiyun# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*4882a593Smuzhiyun%YAML 1.2 3*4882a593Smuzhiyun--- 4*4882a593Smuzhiyun$id: http://devicetree.org/schemas/dsp/fsl,dsp.yaml# 5*4882a593Smuzhiyun$schema: http://devicetree.org/meta-schemas/core.yaml# 6*4882a593Smuzhiyun 7*4882a593Smuzhiyuntitle: NXP i.MX8 DSP core 8*4882a593Smuzhiyun 9*4882a593Smuzhiyunmaintainers: 10*4882a593Smuzhiyun - Daniel Baluta <daniel.baluta@nxp.com> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyundescription: | 13*4882a593Smuzhiyun Some boards from i.MX8 family contain a DSP core used for 14*4882a593Smuzhiyun advanced pre- and post- audio processing. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyunproperties: 17*4882a593Smuzhiyun compatible: 18*4882a593Smuzhiyun enum: 19*4882a593Smuzhiyun - fsl,imx8qxp-dsp 20*4882a593Smuzhiyun - fsl,imx8qm-dsp 21*4882a593Smuzhiyun - fsl,imx8mp-dsp 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun reg: 24*4882a593Smuzhiyun description: Should contain register location and length 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun clocks: 27*4882a593Smuzhiyun items: 28*4882a593Smuzhiyun - description: ipg clock 29*4882a593Smuzhiyun - description: ocram clock 30*4882a593Smuzhiyun - description: core clock 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun clock-names: 33*4882a593Smuzhiyun items: 34*4882a593Smuzhiyun - const: ipg 35*4882a593Smuzhiyun - const: ocram 36*4882a593Smuzhiyun - const: core 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun power-domains: 39*4882a593Smuzhiyun description: 40*4882a593Smuzhiyun List of phandle and PM domain specifier as documented in 41*4882a593Smuzhiyun Documentation/devicetree/bindings/power/power_domain.txt 42*4882a593Smuzhiyun maxItems: 4 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun mboxes: 45*4882a593Smuzhiyun description: 46*4882a593Smuzhiyun List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB 47*4882a593Smuzhiyun (see mailbox/fsl,mu.txt) 48*4882a593Smuzhiyun maxItems: 4 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun mbox-names: 51*4882a593Smuzhiyun items: 52*4882a593Smuzhiyun - const: txdb0 53*4882a593Smuzhiyun - const: txdb1 54*4882a593Smuzhiyun - const: rxdb0 55*4882a593Smuzhiyun - const: rxdb1 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun memory-region: 58*4882a593Smuzhiyun description: 59*4882a593Smuzhiyun phandle to a node describing reserved memory (System RAM memory) 60*4882a593Smuzhiyun used by DSP (see bindings/reserved-memory/reserved-memory.txt) 61*4882a593Smuzhiyun maxItems: 1 62*4882a593Smuzhiyun 63*4882a593Smuzhiyunrequired: 64*4882a593Smuzhiyun - compatible 65*4882a593Smuzhiyun - reg 66*4882a593Smuzhiyun - clocks 67*4882a593Smuzhiyun - clock-names 68*4882a593Smuzhiyun - power-domains 69*4882a593Smuzhiyun - mboxes 70*4882a593Smuzhiyun - mbox-names 71*4882a593Smuzhiyun - memory-region 72*4882a593Smuzhiyun 73*4882a593SmuzhiyunadditionalProperties: false 74*4882a593Smuzhiyun 75*4882a593Smuzhiyunexamples: 76*4882a593Smuzhiyun - | 77*4882a593Smuzhiyun #include <dt-bindings/firmware/imx/rsrc.h> 78*4882a593Smuzhiyun #include <dt-bindings/clock/imx8-clock.h> 79*4882a593Smuzhiyun dsp@596e8000 { 80*4882a593Smuzhiyun compatible = "fsl,imx8qxp-dsp"; 81*4882a593Smuzhiyun reg = <0x596e8000 0x88000>; 82*4882a593Smuzhiyun clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>, 83*4882a593Smuzhiyun <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>, 84*4882a593Smuzhiyun <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>; 85*4882a593Smuzhiyun clock-names = "ipg", "ocram", "core"; 86*4882a593Smuzhiyun power-domains = <&pd IMX_SC_R_MU_13A>, 87*4882a593Smuzhiyun <&pd IMX_SC_R_MU_13B>, 88*4882a593Smuzhiyun <&pd IMX_SC_R_DSP>, 89*4882a593Smuzhiyun <&pd IMX_SC_R_DSP_RAM>; 90*4882a593Smuzhiyun mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1"; 91*4882a593Smuzhiyun mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>; 92*4882a593Smuzhiyun memory-region = <&dsp_reserved>; 93*4882a593Smuzhiyun }; 94