1* rk3399 dram default timing is at arch/arm64/boot/dts/rk3399_dram_default_timing.dtsi 2 3Required properties: 4- compatible : Should be "rockchip,ddr-timing" 5 6- ddr3_speed_bin : Value is defined at include/dt-bindings/clock/ddr.h. 7 It select DDR3 cl-trp-trcd type, default value "DDR3_DEFAULT".it must selected 8 according to "Speed Bin" in DDR3 datasheet, DO NOT use smaller "Speed Bin" than 9 DDR3 exactly is. 10 11- pd_idle : Defines the power-down mode auto entry controller clocks. 12 This parameter defines the number of idle controller clocks that can elapse 13 before the controller will automatically issue an entry into the appropriate 14 power-down low power state. 15 16- sr_idle : Defines the Self-Refresh or Self-Refresh with Memory Clock Gating 17 auto entry periodic cycles. 18 This parameter defines the number of long count sequences that can elapse 19 before the controller will automatically issue an entry into the Self-Refresh 20 or Self-Refresh with Memory Clock Gating low power state. 21 22- sr_mc_gate_idle : Defined the Self-Refresh with Memory and Controller Clock Gating 23 auto entry periodic cycles. 24 This parameter defines the number of long count sequences that can elapse before 25 the controller will automatically issue an entry into the Self-Refresh with 26 Memory and Controller Clock Gating low power state. 27 28- srpd_lite_idle : Define the Lite Self-Refresh Power-Down auto entry periodic 29 cycles. 30 This parameter defines the number of long count sequences that can elapse 31 before the controller will automatically issue an entry into the 32 Lite Self-Refresh Power-Down low power state. 33 34- standby_idle : Define the standby mode auto entry periodic cycles. 35 36- auto_lp_dis_freq : It's defined the auto low down mode frequency in MHz (Mega Hz), 37 when ddr freq greater than or equal this setting value, auto power-down will disable. 38 39- ddr3_dll_dis_freq : It's defined the DDR3 dll bypass frequency in MHz (Mega Hz), 40 when ddr freq less than or equal this setting value, DDR3 dll will bypssed. 41 note: if dll was bypassed, the odt also stop working. 42 43- phy_dll_dis_freq : Defined the PHY dll bypass frequency in MHz (Mega Hz), 44 when ddr freq less than or equal this setting value, phy dll will bypssed. 45 note: phy dll and phy odt are independent. 46 47- ddr3_odt_dis_freq : Defined the DDR3 odt disable frequency in 48 MHz (Mega Hz), when ddr frequency less then or equal ethis setting value, the DDR3 49 ODT are disabled. 50 51- ddr3_drv : Define the driver strength in ohm when connect DDR3. 52 53- ddr3_odt : Define the ODT in ohm when connect DDR3. 54 55- phy_ddr3_ca_drv : Define the PHY CA driver strength in ohm when connect DDR3. 56 57- phy_ddr3_dq_drv : Define the PHY DQ driver strength in ohm when connect DDR3. 58 59- phy_ddr3_odt : Define the phy odt in ohm when connect DDR3. 60 61- lpddr3_odt_dis_freq : Defined the LPDDR3 odt disable frequency in 62 MHz (Mega Hz), when ddr frequency less or equal then this setting value, the LPDDR3 63 ODT are disabled. 64 65- lpddr3_drv : Define the driver strength in ohm when connect LPDDR3. 66 67- lpddr3_odt : Define the ODT in ohm when connect LPDDR3. 68 69- phy_lpddr3_ca_drv : Define the PHY CA driver strength in ohm when connect LPDDR3. 70 71- phy_lpddr3_dq_drv : Define the PHY DQ driver strength in ohm when connect LPDDR3. 72 73- phy_lpddr3_odt : Define the phy odt in ohm when connect LPDDR3. 74 75- lpddr4_odt_dis_freq : Defined the LPDDR4 odt disable frequency in 76 MHz (Mega Hz), when ddr frequency less or equal then this setting value, the LPDDR4 77 ODT are disabled. 78 79- lpddr4_drv : Define the driver strength in ohm when connect LPDDR4. 80 81- lpddr4_dq_odt : Define the DQ ODT in ohm when connect LPDDR4. 82 83- lpddr4_ca_odt : Define the CA ODT in ohm when connect LPDDR4. 84 85- phy_lpddr4_ca_drv : Define the PHY CA driver strength in ohm when connect LPDDR4. 86 87- phy_lpddr4_ck_cs_drv : Define the PHY CLK and CS driver strength in ohm when connect LPDDR4. 88 89- phy_lpddr4_dq_drv : Define the PHY DQ driver strength in ohm when connect LPDDR4. 90 91- phy_lpddr4_odt : Define the phy odt in ohm when connect LPDDR4. 92 93Example: 94/ { 95 ddr_timing: ddr_timing { 96 compatible = "rockchip,ddr-timing"; 97 ddr3_speed_bin = <21>; 98 pd_idle = <0>; 99 sr_idle = <0>; 100 sr_mc_gate_idle = <0>; 101 srpd_lite_idle = <0>; 102 standby_idle = <0>; 103 auto_lp_dis_freq = <666>; 104 ddr3_dll_dis_freq = <300>; 105 phy_dll_dis_freq = <260>; 106 107 ddr3_odt_dis_freq = <666>; 108 ddr3_drv = <DDR3_DS_40ohm>; 109 ddr3_odt = <DDR3_ODT_120ohm>; 110 phy_ddr3_ca_drv = <PHY_DRV_ODT_40>; 111 phy_ddr3_dq_drv = <PHY_DRV_ODT_40>; 112 phy_ddr3_odt = <PHY_DRV_ODT_240>; 113 114 lpddr3_odt_dis_freq = <666>; 115 lpddr3_drv = <LP3_DS_34ohm>; 116 lpddr3_odt = <LP3_ODT_240ohm>; 117 phy_lpddr3_ca_drv = <PHY_DRV_ODT_34_3>; 118 phy_lpddr3_dq_drv = <PHY_DRV_ODT_34_3>; 119 phy_lpddr3_odt = <PHY_DRV_ODT_240>; 120 121 lpddr4_odt_dis_freq = <933>; 122 lpddr4_drv = <LP4_PDDS_60ohm>; 123 lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>; 124 lpddr4_ca_odt = <LP4_CA_ODT_40ohm>; 125 phy_lpddr4_ca_drv = <PHY_DRV_ODT_40>; 126 phy_lpddr4_ck_cs_drv = <PHY_DRV_ODT_80>; 127 phy_lpddr4_dq_drv = <PHY_DRV_ODT_80>; 128 phy_lpddr4_odt = <PHY_DRV_ODT_60>; 129 }; 130}; 131