xref: /OK3568_Linux_fs/kernel/Documentation/devicetree/bindings/dma/xilinx/zynqmp_dma.txt (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593SmuzhiyunXilinx ZynqMP DMA engine, it does support memory to memory transfers,
2*4882a593Smuzhiyunmemory to device and device to memory transfers. It also has flow
3*4882a593Smuzhiyuncontrol and rate control support for slave/peripheral dma access.
4*4882a593Smuzhiyun
5*4882a593SmuzhiyunRequired properties:
6*4882a593Smuzhiyun- compatible		: Should be "xlnx,zynqmp-dma-1.0"
7*4882a593Smuzhiyun- reg			: Memory map for gdma/adma module access.
8*4882a593Smuzhiyun- interrupts		: Should contain DMA channel interrupt.
9*4882a593Smuzhiyun- xlnx,bus-width	: Axi buswidth in bits. Should contain 128 or 64
10*4882a593Smuzhiyun- clock-names		: List of input clocks "clk_main", "clk_apb"
11*4882a593Smuzhiyun			  (see clock bindings for details)
12*4882a593Smuzhiyun
13*4882a593SmuzhiyunOptional properties:
14*4882a593Smuzhiyun- dma-coherent		: Present if dma operations are coherent.
15*4882a593Smuzhiyun
16*4882a593SmuzhiyunExample:
17*4882a593Smuzhiyun++++++++
18*4882a593Smuzhiyunfpd_dma_chan1: dma@fd500000 {
19*4882a593Smuzhiyun	compatible = "xlnx,zynqmp-dma-1.0";
20*4882a593Smuzhiyun	reg = <0x0 0xFD500000 0x1000>;
21*4882a593Smuzhiyun	interrupt-parent = <&gic>;
22*4882a593Smuzhiyun	interrupts = <0 117 4>;
23*4882a593Smuzhiyun	clock-names = "clk_main", "clk_apb";
24*4882a593Smuzhiyun	xlnx,bus-width = <128>;
25*4882a593Smuzhiyun	dma-coherent;
26*4882a593Smuzhiyun};
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